SWRS283A June   2022  – November 2022 IWR6243

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 8.9.5.1 I2C Timing Requirements
      6. 8.9.6 LVDS Interface Configuration
        1. 8.9.6.1 LVDS Interface Timings
      7. 8.9.7 General-Purpose Input/Output
        1. 8.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.9.8 Camera Serial Interface (CSI2)
        1. 8.9.8.1 CSI2 Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
      2. 9.4.2 ADC Channels (Service) for User Application
        1. 9.4.2.1 GPADC Parameters
  10. 10Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Radar Sensor for Industrial Applications
    3. 11.3 Imaging Radar using Cascade Configuration
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Export Control Notice
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2.     Package Option Addendum
    3. 13.2 Tape and Reel Information
    4.     Tray Information
    5.     Mechanical Data

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
  • ABL|161
サーマルパッド・メカニカル・データ
発注情報

8.6 Power Consumption Summary

#GUID-8BF7260D-5CCE-4E23-83F3-FB0E5AE6243A/X5427 and #GUID-8BF7260D-5CCE-4E23-83F3-FB0E5AE6243A/X5427-2 summarize the power consumption at the power terminals.

Table 8-3 Maximum Current Ratings at Power Terminals
PARAMETER(2)SUPPLY NAMEDESCRIPTIONMINTYPMAXUNIT
Current consumptionVDDIN, VIN_SRAM, VNWATotal current drawn by all nodes driven by 1.2V rail

850

mA
VIN_13RF1, VIN_13RF2Total current drawn by all nodes driven by 1.3V (or 1V in LDO Bypass mode) rail when 3 transmitters are used (1)

2500

VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCOTotal current drawn by all nodes driven by 1.8V rail

850

VIOINTotal current drawn by all nodes driven by 3.3V rail(3)

50

(1) Three transmitters can simultaneously be deployed in the device with 1V / LDO bypass and PA LDO disable mode. In this mode 1V supply needs to be fed on the VOUT PA pin. For a 2Tx use case, the peak 1V supply current goes up to 2000 mA.
(2) The specified current values are at typical supply voltage level.
(3) The exact VIOIN current depends on the peripherals used and their frequency of operation.
Table 8-4 Average Power Consumption at Power Terminals
PARAMETERCONDITIONDESCRIPTIONMINTYPMAXUNIT
Average power consumption in single chip mode.1.0-V internal LDO bypass mode1TX, 4RXThe frame is set to 50% duty cycle. 4lane CSI interface is enabled at 600Mbps for ADC data transfer

1.41

W
2TX, 4RX

1.52

3TX, 4RX

1.65

Average power consumption in cascade mode for primary sensor. 1.0-V internal LDO bypass mode 3TX, 4RX The frame is set to 50% duty cycle. 4lane CSI interface is enabled at 600Mbps for ADC data transfer 1.71 W
Average power consumption in cascade mode for secondary sensor. 1.0-V internal LDO bypass mode 3TX, 4RX The frame is set to 50% duty cycle. 4lane CSI interface is enabled at 600Mbps for ADC data transfer 1.62 W