SWRS323 November   2023  – April 2024 IWRL6432AOP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configurations and Functions
    1. 6.1 Pin Diagrams
    2.     10
    3. 6.2 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
      12.      23
      13.      24
      14.      25
      15.      26
      16.      27
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.5.2 Hardware Requirements
      3. 7.5.3 Impact to Your Hardware Warranty
    6. 7.6  Power Supply Specifications
      1. 7.6.1 Power Optimized 3.3V I/O Topology
      2. 7.6.2 Power Optimized 1.8V I/O Topology
      3. 7.6.3 BOM Optimized 3.3V I/O Topology
      4. 7.6.4 BOM Optimized 1.8V I/O Topology
      5. 7.6.5 System Topologies
        1. 7.6.5.1 Power Topologies
          1. 7.6.5.1.1 BOM Optimized Mode
          2. 7.6.5.1.2 Power Optimized Mode
      6. 7.6.6 Internal LDO output decoupling capacitor and layout conditions for BOM optimized topology
        1. 7.6.6.1 Single-capacitor rail
          1. 7.6.6.1.1 1.2V Digital LDO
        2. 7.6.6.2 Two-capacitor rail
          1. 7.6.6.2.1 1.2V RF LDO
          2. 7.6.6.2.2 1.2V SRAM LDO
          3. 7.6.6.2.3 1.0V RF LDO
      7. 7.6.7 Noise and Ripple Specifications
    7. 7.7  Power Save Modes
      1. 7.7.1 Typical Power Consumption Numbers
    8. 7.8  Peak Current Requirement per Voltage Rail
    9. 7.9  Supported DFE Features
    10. 7.10 RF Specification
    11. 7.11 CPU Specifications
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 Antenna Radiation Patterns
      1. 7.13.1 Antenna Radiation Patterns for Receiver
      2. 7.13.2 Antenna Radiation Patterns for Transmitter
    14. 7.14 Antenna Positions
    15. 7.15 Timing and Switching Characteristics
      1. 7.15.1  Power Supply Sequencing and Reset Timing
      2. 7.15.2  Synchronized Frame Triggering
      3. 7.15.3  Input Clocks and Oscillators
        1. 7.15.3.1 Clock Specifications
      4. 7.15.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 7.15.4.1 McSPI Features
        2. 7.15.4.2 SPI Timing Conditions
        3. 7.15.4.3 SPI—Controller Mode
          1. 7.15.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 7.15.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 7.15.4.4 SPI—Peripheral Mode
          1. 7.15.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 7.15.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 7.15.5  RDIF Interface Configuration
        1. 7.15.5.1 RDIF Interface Timings
        2. 7.15.5.2 RDIF Data Format
      6. 7.15.6  General-Purpose Input/Output
        1. 7.15.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 7.15.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.15.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.15.8  Serial Communication Interface (SCI)
        1. 7.15.8.1 SCI Timing Requirements
      9. 7.15.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.15.9.1 I2C Timing Requirements
      10. 7.15.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.15.10.1 QSPI Timing Conditions
        2. 7.15.10.2 Timing Requirements for QSPI Input (Read) Timings
        3. 7.15.10.3 QSPI Switching Characteristics
      11. 7.15.11 JTAG Interface
        1. 7.15.11.1 JTAG Timing Conditions
        2. 7.15.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.15.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
      2. 8.3.2 Clock Subsystem
      3. 8.3.3 Transmit Subsystem
      4. 8.3.4 Receive Subsystem
      5. 8.3.5 Processor Subsystem
      6. 8.3.6 Host Interface
      7. 8.3.7 Application Subsystem Cortex-M4F
      8. 8.3.8 Hardware Accelerator (HWA1.2) Features
        1. 8.3.8.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 8.4 Other Subsystems
      1. 8.4.1 GPADC Channels (Service) for User Application
      2. 8.4.2 GPADC Parameters
    5. 8.5 Memory Partitioning Options
    6. 8.6 Boot Modes
  10. 9 Monitoring and Diagnostics
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • AMY|101
サーマルパッド・メカニカル・データ
発注情報

Table 6-1 Pin Attributes (AMY0101A Package)
BGA BALL NUMBER(1) BALL NAME(2) SIGNAL NAME(3) PINCNTL REGISTER(4) PINCNTL REGISTER ADDRESS(5)(11) MODE(6) TYPE(7) BALL STATE DURING RST(8) BALL RESET AFTER RST(9) PULL UP/DOWN TYPE(10)
B10CLKMCLKMA
D10CLKPCLKPA
M10GPADC1GPADC1A
H2 GPIO_2 GPIO_2PADAL_CFG_REG 0x5A00 002C 0IOOff / Off / Off Off / Off / Off PU/PD
LIN_RX1I
WARM_RESET_OUT2O
I2C_SDA3IO
SPIA_CS1_N4IO
WU_REQIN5I
RTC_CLK_IN6I
MDO_D07O
J2 GPIO_5 GPIO_5PADAV_CFG_REG 0x5A00 0054 0IOOff / Off / Off Off / Off / Off PU/PD
SYNC_IN1I
LIN_RX2I
EPWMB3O
EPWM_SYNC_IN4I
MDO_D35O
L3 HOST_CLK_REQ HOST_CLK_REQPADAX_CFG_REG 0x5A00 005C 0OOff / Off / Off Off / SS / Off PU/PD
GPIO_71IO
MCU_CLKOUT2O
LIN_TX3O
WU_REQIN4I
SPIB_MISO5IO
I2C_SCL6IO
MDO_D38O
MDO_FRM_CLK9O
J4 NERROR_OUT NERROR_OUTPADAU_CFG_REG 0x5A00 0050 0OOff / Off / Off Off / Off / Off PU/PD
GPIO_41IO
SYNC_IN2I
SPIB_CS0_N3IO
WU_REQIN4I
RTC_CLK_IN5I
MCU_CLKOUT6O
MDO_D37O
M3, M4NRESETNRESETA
A8, B8OSC_CLK_OUTOSC_CLK_OUTA
H3 PMIC_CLKOUT SOP[1] PADAK_CFG_REG 0x5A00 0028 During Power-up I Off / Off / Off Off / Off / Off PU/PD
PMIC_CLKOUT 0 O
LIN_TX1O
SPIA_CS1_N2IO
MDO_FRM_CLK3O
C2 QSPI[0] QSPI[0]PADAC_CFG_REG 0x5A00 0008 0IOOff / Off / Off Off / Off / Off PU/PD
SPIB_MOSI1IO
MDO_D02O
C3 QSPI[1] QSPI[1]PADAD_CFG_REG 0x5A00 000C 0IOff / Off / Off Off / Off / Off PU/PD
SPIB_MISO1IO
RTC_CLK_IN2I
MDO_D33O
C4 QSPI[2] QSPI[2]PADAE_CFG_REG 0x5A00 0010 0IOff / Off / Off Off / Off / Off PU/PD
I2C_SCL1IO
WU_REQIN2I
MDO_D13O
B3, B4 QSPI[3] QSPI[3]PADAF_CFG_REG 0x5A00 0014 0IOff / Off / Off Off / Off / Off PU/PD
I2C_SDA1IO
SYNC_IN2I
MDO_D23O
D2 QSPI_CLK QSPI_CLKPADAA_CFG_REG 0x5A00 0000 0IOOff / Off / Off Off / Off / Off PU/PD
SPIB_CLK1IO
MDO_CLK2O
D3 QSPI_CS QSPI_CSPADAB_CFG_REG 0x5A00 0004 0OOff / Off / Off Off / Off / Off PU/PD
SPIB_CS0_N1IO
MDO_FRM_CLK2O
G2 RS232_RX RS232_RXPADAP_CFG_REG 0x5A00 003C 0IOff / Off / Up On / Off / Up PU/PD
I2C_SDA1IO
UARTB_RX2I
LIN_RX3I
MDO_D24O
SPIB_MISO5IO
H4 RS232_TX RS232_TXPADAO_CFG_REG 0x5A00 0038 0OOff / Off / Off Off / SS / Off PU/PD
I2C_SCL1IO
UARTB_TX2O
LIN_TX3O
EPWM_SYNC_IN4I
MDO_D15O
SPIB_CS1_N6IO
F1 SPIA_CLK SPIA_CLKPADAG_CFG_REG 0x5A00 0018 0IOOff / Off / Off Off / Off / Off PU/PD
EPWMB1O
I2C_SCL2IO
SPIB_CLK3IO
MDO_CLK4O
F4 SPIA_CS0_N SPIA_CS0_NPADAH_CFG_REG 0x5A00 001C 0IOOff / Off / Off Off / Off / Off PU/PD
EPWMA1O
I2C_SDA2IO
SPIB_CS0_N3IO
MDO_D34O
E4 SPIA_MISO SPIA_MISOPADAJ_CFG_REG 0x5A00 0024 0IOOff / Off / Off Off / Off / Off PU/PD
GPIO_11IO
EPWMA2O
SPIB_MISO3IO
MDO_D24O
E3 SPIA_MOSI SPIA_MOSIPADAI_CFG_REG 0x5A00 0020 0IOOff / Off / Off Off / Off / Off PU/PD
GPIO_01IO
EPWMB2O
SPIB_MOSI3IO
MDO_D14O
F3 TCK TCKPADAT_CFG_REG 0x5A00 004C 0IOff / Off / Down On / Off / Down PU/PD
EPWMB1O
SPIB_CS1_N2IO
SPIB_MOSI3IO
MDO_D04O
F2 TDI TDIPADAR_CFG_REG 0x5A00 0044 0IOff / Off / Down On / Off / Down PU/PD
EPWMA1O
SPIB_CS0_N2IO
E2 TDO SOP[0] PADAS_CFG_REG 0x5A00 0048 During Power-up I Off / Off / Off Off / SS / Off PU/PD
TDO 0 O
MDO_FRM_CLK1O
G3 TMS TMSPADAQ_CFG_REG 0x5A00 0040 0IOff / Off / Up On / Off / Up PU/PD
WARM_RESET_OUT1O
SPIA_CS1_N2IO
SYNC_IN3I
SPIB_MISO4IO
SPIB_CLK5IO
RTC_CLK_IN6I
EPWM_SYNC_IN7I
EPWM_SYNC_OUT8O
L4 UARTA_RTS UARTA_RTSPADAW_CFG_REG 0x5A00 0058 0OOff / Off / Off Off / Off / Off PU/PD
GPIO_61IO
LIN_TX2O
SPIB_CLK3IO
WU_REQIN4I
EPWMA5O
RTC_CLK_IN6I
MDO_CLK7O
J3 UARTA_RX UARTA_RXPADAM_CFG_REG 0x5A00 0030 0IOff / Off / Off Off / Off / Off PU/PD
GPIO_31IO
LIN_RX2I
CAN_FD_RX3I
SYNC_IN4I
UARTB_RX5I
I2C_SDA6IO
MDO_D17O
K3 UARTA_TX UARTA_TXPADAN_CFG_REG 0x5A00 0034 0OOff / Off / Off Off / Off / Off PU/PD
LIN_TX1O
CAN_FD_TX2O
SPIB_MOSI3IO
WU_REQIN4I
UARTB_TX5O
I2C_SCL6IO
MDO_D27O
H10VBGAPVBGAPA
K2VDDVDDPWR
C7, K10, K7, K8, K9VDDA_10RFVDDA_10RFPWR
L10, L7, L8, L9VDDA_12RFVDDA_12RFPWR
M7, M8, M9, N10, N6, N7, N8, N9VDDA_18BBVDDA_18BBPWR
F10, F9VDDA_18VCOVDDA_18VCOPWR
M1VDD_SRAMVDD_SRAMPWR
H7, H8VIN_18PMVIN_18PMPWR
C1, J1VIOINVIOINPWR
B1, L1, L2VIOIN_18VIOIN_18PWR
D7VIOIN_18CLKVIOIN_18CLKPWR
M2, N2VNWAVNWAPWR
G8VOUT_14APLLVOUT_14APLLPWR
F7VOUT_14SYNTHVOUT_14SYNTHPWR
A2, B2VPPVPPPWR
A1, A3, A4, A5, E1, H1, N1, N3, N4, N5VSSVSSGND
A10, A6, A7, A9, B7, B9, C10, C8, C9, D8, D9, E10, E7, E8, E9, F8, G10, G9, H9, J10, J7, J8, J9VSSAVSSAGND
(1) BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
(2) BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
(3) SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
(4) PINCNTL_REGISTER: APPSS Register name for PinMux Control
(5) PINCNTL ADDRESS: APPSS Address for PinMux Control
(6) MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
(7) TYPE: Signal type and direction:
  • I = Input
  • O = Output
  • IO = Input or Output
(8) BALL STATE DURING RST: State of Ball during reset in the format of RX/TX/Pull Status
  • RX (Input buffer)
    • Off: The input buffer is disabled.
    • On: The input buffer is enabled.
  • TX (Output buffer)
    • Off: The output buffer is disabled.
    • Low: The output buffer is enabled and drives VOL.
  • Pull Status (Internal pull resistors)
    • Off: Internal pull resistors are turned off.
    • Up: Internal pull-up resistor is turned on.
    • Down: Internal pull-down resistor is turned on.
    • NA: No internal pull resistor.
  • An empty box, or "-" means Not Applicable.
(9) BALL STATE AFTER RST: State of Ball after reset in the format of RX/TX/Pull Status
  • RX (Input buffer)
    • Off: The input buffer is disabled.
    • On: The input buffer is enabled.
  • TX (Output buffer)
    • Off: The output buffer is disabled.
    • SS: The subsystem selected with MUXMODE determines the output buffer state.
  • Pull status (Internal pull resistors)
    • Off: Internal pull resistors are turned off.
    • Up: Internal pull-up resistor is turned on.
    • Down: Internal pull-down resistor is turned on.
    • NA: No internal pull resistor.
  • An empty box, NA, or "-" means Not Applicable.
(10) PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  • Pull Up: Internal pullup
  • Pull Down: Internal pulldown
  • An empty box means No pull.
(11) Pin Mux Control Value maps to lower 4 bits of register.