SWRS311 December 2024 IWRL6432W
PRODUCTION DATA
The IWRL6432W clock subsystem generates 57 to 63.9GHz from an input reference from a crystal. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an X3 multiplier to create the required frequency in the 57 to 63.9 spectrum. The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
Figure 8-2 describes the clock subsystem.