JAJSI72 November 2019 LDC1001
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN(3) | TYP(4) | MAX(3) | UNIT | |
---|---|---|---|---|---|---|
POWER | ||||||
VDD | Analog supply voltage | 4.75 | 5 | 5.25 | V | |
VIO | IO supply voltage | VIO ≤ VDD | 1.8 | 3.3 | 5.25 | V |
IDD | Supply current on VDD pin | PWR_MODE = 1, no sensor connected | 1.7 | 2.3 | mA | |
IVIO | IO supply current | Static current | 14 | µA | ||
IDD_LP | Standby mode supply current on VDD pin | PWR_MODE = 0, no sensor connected | 250 | µA | ||
tSTART | Start-up time | From POR to ready-to-convert. | 2 | ms | ||
LDC | ||||||
ƒSENSOR_MIN | Minimum sensor frequency | 5 | kHz | |||
ƒSENSOR_MAX | Maximum sensor frequency | 5 | MHz | |||
ASENSOR_MIN | Minimum sensor amplitude | 1 | VPP | |||
ASENSOR_MAX | Maximum sensor amplitude | 4 | VPP | |||
tREC | Recovery time | Oscillation start-up time after RP under-range condition | 10 | 1/ƒsensor | ||
RP_MIN | Minimum sensor RP range | 798 | Ω | |||
RP_MAX | Maximum sensor RP range | 3.93 | MΩ | |||
RP_RES | RP measurement resolution | 16 | Bits | |||
L Res | Inductance measurement resolution | RESPONSE_TIME = b111 (6144), ƒEXT = 8 MHz, ƒSENSOR = 5 kHz | 24 | Bits | ||
tS_MIN | Minimum response time | Minimum programmable settling time of digital filter | 192/ƒSENSOR | s | ||
tS_MAX | Maximum response time | Maximum programmable settling time of digital filter | 6144/ƒSENSOR | s | ||
EXTERNAL CLOCK FOR FREQUENCY COUNTER | ||||||
External Clock | Frequency | 8 | MHz | |||
Clock input high voltage | VIO | V | ||||
DIGITAL I/O CHARACTERISTICS | ||||||
VIH | Logic 1 input voltage | 0.8 × VIO | V | |||
VIL | Logic 0 input voltage | 0.2 × VIO | V | |||
VOH | Logic 1 output voltage | ISOURCE = 400 µA | VIO–0.3 | V | ||
VOL | Logic 0 output voltage | ISINK = 400 µA | 0.3 | V | ||
IIOHL | Digital IO leakage current | –500 | 500 | nA |