JAJSGO3C december   2018  – july 2023 LDC5072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Diagnostics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Supply Voltage
      2. 8.3.2 Excitation Signal
      3. 8.3.3 Signal Processing Block
        1. 8.3.3.1 Demodulation
        2. 8.3.3.2 Fixed Gain Control
        3. 8.3.3.3 Automatic Gain Control
      4. 8.3.4 Output Stage
      5. 8.3.5 Diagnostics
        1. 8.3.5.1 Undervoltage Diagnostics
        2. 8.3.5.2 Initialization Diagnostics
        3. 8.3.5.3 Normal State Diagnostics
        4. 8.3.5.4 Fault State Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 IDLE State
      2. 8.4.2 DIAGNOSTICS State
      3. 8.4.3 NORMAL State
      4. 8.4.4 FAULT State
      5. 8.4.5 DISABLED State
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 5-V Supply Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VREG and VCC
          2. 9.2.1.2.2 Output Capacitors
          3. 9.2.1.2.3 AGC Mode
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3.3-V Supply Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VREG and VCC
          2. 9.2.2.2.2 Output Capacitors
          3. 9.2.2.2.3 Fixed Gain Mode
      3. 9.2.3 Redundancy Mode
      4. 9.2.4 Single-Ended Mode
      5. 9.2.5 External Diagnostics Required for Loss of VCC or GND
  11. 10Power Supply Recommendations
    1. 10.1 Mode 1: VCC = 5 V, VREG = 3.3 V
    2. 10.2 Mode 2: VCC = VREG = 3.3 V
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5.2 Initialization Diagnostics

During power up in the DIAGNOSTICS state, the LDC5072-Q1 undergoes a number of self-diagnostics and checks (for fault thresholds refer to Diagnostics and for de-glitch times refer to Switching Characteristics ):

  1. EEPROM CRC check: the LDC5072-Q1 calculates the CRC value of the EEPROM register settings and compares it to the recorded expected CRC value. In case of FAULT, the LDC5072-Q1 transitions to the DISABLED state.
  2. LBIST check: the LDC5072-Q1 undergoes automated self-testing pattern for the digital logic. In case of FAULT, the LDC5072-Q1 transitions to the DISABLED state.
  3. ABIST check: the LDC5072-Q1 undergoes automated self-testing pattern for the fault-monitoring circuits. In case of FAULT, the LDC5072-Q1 transitions to the DISABLED state.
  4. Sensor interface BIST check: the LDC5072-Q1 applies the automated test patterns to Sensor interface (LCIN, LCOUT, IN0P, IN0N, IN1P, and IN1N) pins to check that they are open or shorted to GND or battery. It also checks if there is a short between the coils of the sensor and if any of the coils are open. The LDC5072-Q1 will also check if any impedance is present as specified by the RAGC_EN_AUTO or RPU_AGC_EN on the AGC_EN pin and check if the AGC_EN pin is not shorted to GND.
  5. VREG cap loss check: the LDC5072-Q1 uses the VREG cap to compare the internal time constant with the external time constant (5-V VCC mode only). This check is only performed at power up and is not performed if the device transitions from FAULT state to DIAGNOSTICS state. The maximum capacitance on VREG pin that can trigger this fault is given by CLOSS_VREG.
  6. The LDC5072-Q1 enables the LC oscillator and checks that VUVL_AMP_LC, VOVH_AMP_LC, VUVL_CM_LC, and VOVH_CM_LC faults disappear within tLC_FLT_DT.
  7. The LDC5072-Q1 enables the AFE, AGC, and Output stages in a staggered manner.
  8. The LDC5072-Q1 the device resets all checks and faults for certain period of time to allow all internal signals to settle and then starts monitor faults
  9. The LDC5072-Q1 transitions to the Normal state ensuring that tPR‎WR_ON is met and no other faults are detected. In AUTO AGC mode, the LDC5072-Q1 also checks that the output of the AGC block is within AGC_Target. If the AGC block is not within AGC_Target, the devices transitions to the DISABLED state.