JAJSGO3C december   2018  – july 2023 LDC5072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Diagnostics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Supply Voltage
      2. 8.3.2 Excitation Signal
      3. 8.3.3 Signal Processing Block
        1. 8.3.3.1 Demodulation
        2. 8.3.3.2 Fixed Gain Control
        3. 8.3.3.3 Automatic Gain Control
      4. 8.3.4 Output Stage
      5. 8.3.5 Diagnostics
        1. 8.3.5.1 Undervoltage Diagnostics
        2. 8.3.5.2 Initialization Diagnostics
        3. 8.3.5.3 Normal State Diagnostics
        4. 8.3.5.4 Fault State Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 IDLE State
      2. 8.4.2 DIAGNOSTICS State
      3. 8.4.3 NORMAL State
      4. 8.4.4 FAULT State
      5. 8.4.5 DISABLED State
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 5-V Supply Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VREG and VCC
          2. 9.2.1.2.2 Output Capacitors
          3. 9.2.1.2.3 AGC Mode
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3.3-V Supply Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VREG and VCC
          2. 9.2.2.2.2 Output Capacitors
          3. 9.2.2.2.3 Fixed Gain Mode
      3. 9.2.3 Redundancy Mode
      4. 9.2.4 Single-Ended Mode
      5. 9.2.5 External Diagnostics Required for Loss of VCC or GND
  11. 10Power Supply Recommendations
    1. 10.1 Mode 1: VCC = 5 V, VREG = 3.3 V
    2. 10.2 Mode 2: VCC = VREG = 3.3 V
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4 Device Functional Modes

The LDC5072-Q1 is driven by a state machine. The state machine is initialized upon power up, and the machine goes through the initial diagnostics routines. If the system functions normally, the device moves to a normal operational state and starts to drive the OUT pin to indicate angular information. In case of a fault, the device moves to the FAULT state, the LC oscillator driver is disabled, and the OUT pins are tri-stated to indicate fault condition until the FAULT condition is removed or the IC is power-cycled. Some critical faults will lead to the disabled state, which requires a power-cycle to recover.

Figure 8-5 shows the different device states. The management of faults is divided into four types of faults as shown in Table 8-1:

  • Initialization faults: These faults occur during initialization and transitions the device to DISABLED state and the device indicates a fault at the OUTx pins.
  • Run Time #1 faults: These faults are checked in NORMAL state and transition the device to FAULT state. For these type of faults, the device will try to recover from FAULT state when the fault condition is removed and by transitioning to the DIAGNOSTIC state.
  • Run Time #2 faults: These faults are critical faults which are checked in NORMAL state and transition to DISABLED state. A recovery is attempted from this state as described in DISABLED StateDISABLED StateDISABLED State.
  • Reset faults: These faults will put the part in reset and the device will power up again once the conditions causing the fault are cleared.

Table 8-1 Diagnostic List
RESET FAULTSINITIALIZATION FAULTSRUN TIME FAULTS # 1RUN TIME FAULTS # 2
VREG UNDER VOLTAGE CHECKEE CRC CHECKVCC OV/UV CHECK(1)CRITICAL REGISTERS REDUNDANCY CHECK
DVDD UNDER VOLTAGE CHECKLBIST CHECKFREQUENCY CHECK REGISTER CRC CHECK
ABIST CHECKLC OSCILLATOR VOLTAGE CHECK TM0 PULL UP CHECK
SENSOR INTERFAFE BIST CHECKPHASE IMBALANCE CHECK T0UT PULL UP CHECK
VREG CAP LOSS CHECKINPUT SIGNAL OUT OF RANGE CHECKAGC_EN TOGGLE CHECK
AGC_EN BIST CHECKOUTPUT SIGNAL OUT OF RANGE CHECK
OUTPUT SIGNAL VOLTAGE CHECK
OUTPUT SIGNAL COMMON MODE CHECK
OUTPUT SHORT CHECK
FREQUENCY IMBALANCE CHECK
TSD CHECK(1)
VREG OV CHECK(1)
(1) These faults force the device to stay in FAULT state and not allow attempt for recovery till the fault causing condition is removed.

Figure 8-5 shows the states and the transitions for the LDC5072-Q1. Following states are considered SAFE state where the device has detected a fault and indicates a fault making all the OUT pins high-impedance:

  • IDLE
  • FAULT
  • DISABLED
In diagnostic state, the device indicates faults till all checks are complete and then drives the OUT pins to correct values.

GUID-3A1BE6DE-C931-45D1-902F-A97F5DF28329-low.gifFigure 8-5 Device State Diagram