JAJSGO3C december   2018  – july 2023 LDC5072-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Diagnostics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Supply Voltage
      2. 8.3.2 Excitation Signal
      3. 8.3.3 Signal Processing Block
        1. 8.3.3.1 Demodulation
        2. 8.3.3.2 Fixed Gain Control
        3. 8.3.3.3 Automatic Gain Control
      4. 8.3.4 Output Stage
      5. 8.3.5 Diagnostics
        1. 8.3.5.1 Undervoltage Diagnostics
        2. 8.3.5.2 Initialization Diagnostics
        3. 8.3.5.3 Normal State Diagnostics
        4. 8.3.5.4 Fault State Diagnostics
    4. 8.4 Device Functional Modes
      1. 8.4.1 IDLE State
      2. 8.4.2 DIAGNOSTICS State
      3. 8.4.3 NORMAL State
      4. 8.4.4 FAULT State
      5. 8.4.5 DISABLED State
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 5-V Supply Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 VREG and VCC
          2. 9.2.1.2.2 Output Capacitors
          3. 9.2.1.2.3 AGC Mode
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3.3-V Supply Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 VREG and VCC
          2. 9.2.2.2.2 Output Capacitors
          3. 9.2.2.2.3 Fixed Gain Mode
      3. 9.2.3 Redundancy Mode
      4. 9.2.4 Single-Ended Mode
      5. 9.2.5 External Diagnostics Required for Loss of VCC or GND
  11. 10Power Supply Recommendations
    1. 10.1 Mode 1: VCC = 5 V, VREG = 3.3 V
    2. 10.2 Mode 2: VCC = VREG = 3.3 V
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Diagnostics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPD_INxN_BIST    Pull down current to GND during startup on INxN pins for sensor BIST 150 200 270 μA
IPU_INxP_BIST Pull up current from VREG during startup on INxP pins for sensor BIST 150 200 270
VTH_FALL_INxP_BIST   Falling threshold of window comparator for sensor BIST on INxP pins 22.7 25 30 %VREG
VTH_FALL_INxN_BIST Falling threshold of window comparator for sensor BIST on INxN pins 70 75 77.3
IPU_AGC_EN_BIST    Pull up current from VREG during startup BIST on AGC_EN pin to check short to ground 200 250 350 μA
VUVUTH_VCC VCC under voltage upper threshold(1) 4.5 V
VUVLTH_VCC VCC under voltage lower threshold(1) 3.6
VOVUTH_VCC VCC over voltage upper threshold 6.5
VOVLTH_VCC VCC over voltage lower threshold 5.6
CLOSS_VREG   VREG external capacitor loss check. Capacitor values below this will trigger a fault. 5V VCC mode only 1 nF
VOVUTH_VREG (3) VREG overvoltage upper threshold 4.2 V
VOVLTH_VREG VREG overvoltage lower threshold 3.6
VPOR_VREG_uth   VREG power-on upper threshold 3.15 V
VPOR_VREG_lth VREG power-on lower thershold 2.91
fFLTH_LC    LC oscillator frequency too high fault detection 5.3 6.2 MHz
fFLTL_LC LC oscillator frequency too low fault detection 2.0 2.4
IPU_LCx_BIST    Pull up current from VREG during startup on LCOUT and LCIN pins for sensor BIST 1.7 2.6 4.0 mA
IPD_LCx_BIST Pull down current to GND during startup on LCOUT and LCIN pins for sensor BIST 1.7 2.6 4.0
tMIN_PH_IMB    Minimum time between zero crossing of sine output and the following zero crossing of cosine output and vice versa to not signal a phase imbalance fault(2). 8.5 10 11.5 μs
VALAGC_INP_OOR_L    AGC quantized step out of 256 (min to max gain) in auto gaib mode to signal FAULT when input signal is very low amplitude 251 AGC code
VALAGC_INP_OOR_H AGC quantized step out of 256 (min to max gain) in auto gain modet o signal FAULT when input signal is very high amplitude 4
VOOR_H_INx_PIN    Out of range single ended fault threshold voltage for each IN pin  - High 70 75 77.3 %VREG
VOOR_L_INx_PIN Out of range single ended fault threshold voltage for each IN pin - Low 22.7 25 30 %VREG
VOOR_H_INx_LPF Out of range single ended fault threshold voltage at low pass filter output - High 87.5 92.5 98 %VREG
VOOR_L_INx_LPF Out of range single ended fault threshold voltage at low pass filter output - Low 1 7.5 12 %VREG
VOOR_H_OUTx_PIN Out of range single ended fault threshold voltage for each OUT pin - High 93 95 97 %VCC
VOOR_L_OUTx_PIN Out of range single ended fault threshold voltage for each OUT pin - Low 3 5 7 %VCC
VCM_H_OUTx_PIN    Deviation of output common mode above VREF_OUT to trigger a FAULT 0.8 10 %VCC
VCM_L_OUTx_PIN Deviation of output common mode below VREF_OUT to trigger a FAULT 0.8 10 %VCC
VOUTx_SHRT_P_CMP_OFF    Offset between internal AGC diffrential output value and OUTxP differential value before short between OUTxP pins is detected. +100 +250 +440 mV
VOUTx_SHRT_N_CMP_OFF  Offset between internal AGC diffrential output value and OUTxN differential value before short between OUTxN pins is detected.  -380 -250 -100 mV
VUV_DVDD    Internal Digital Supply undervoltage check. 1.2 1.3 V
VTOGGLE_AGC_EN    Checks if the comparator on AGC_EN toggles after AGC_EN status determination 50 200 mV
TTSD_rise    Abmient temperature above which thermal shutdown fault is triggered. 190 ℃
TTSD_fall Abmient temperature below which thermal shutdown fault is cleared 160 ℃
(1) Continuously checked in VCC = 5V mode. Ignored in VCC=VREG=3.3V mode
(2) Fault is signaled only at occurance of 3 consecutive violations of the minimum time.
(3) Device will continue normal operation until the over-voltage threshold on VREG triggered