JAJSMD5A February   2023  – September 2023 LM2101

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 機能ブロック図
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select External Bootstrap Diode and Its Series Resistor
        2. 8.2.2.2 Select Bootstrap and GVDD Capacitor
        3. 8.2.2.3 Select External Gate Driver Resistor
        4. 8.2.2.4 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DSG|8
サーマルパッド・メカニカル・データ

8.2.2.2 Select Bootstrap and GVDD Capacitor

The bootstrap capacitor must maintain the VBST-SH voltage above the UVLO threshold for normal operation. Calculate the maximum allowable drop across the bootstrap capacitor with Equation 2.

Equation 2. ∆ V B S T   = V G V D D - V D H - V B S T L = 12 V - 1 V - 8.05 V = 2.95 V

where

  • VGVDD = Supply voltage of the gate drive IC
  • VDH = Bootstrap diode forward voltage drop
  • VBSTL = BST falling threshold (VBSTR(max) - VBSTHYS)

Then, the total charge needed per switching cycle is estimated by Equation 3.

Equation 3. Q T O T A L = Q G + I B S T S × D M A X f S W + I B S T f S W = 17 n C + 33.3 μ A × 0.95 50 k H z + 150 μ A 50 k H z = 20 n C

where

  • QG = Total MOSFET gate charge
  • IBSTS = BST to VSS leakage current
  • DMax = Converter maximum duty cycle
  • IBST = BST quiescent current

Next, use Equation 4 to estimate the minimum bootstrap capacitor value.

Equation 4. C B O O T   ( M I N ) = Q T O T A L ∆ V B S T = 20 n C 2.95 V = 6.8 n F

In practice, the value of the CBoot capacitor must be greater than calculated to allow for situations where the power stage may skip pulse due to load transients. Equation 5 can be used to estimate the recommended bootstrap capacitance based on the maximum bootstrap voltage ripple desired for a specific application.

Equation 5. C B O O T   > Q T O T A L ∆ V B S T _ R I P P L E

where

  • ∆VBST_RIPPLE = Maximum allowable voltage drop across the bypass capacitor based on system requirements

TI recommends having enough margins and to place the bootstrap capacitor as close to the BST and SH pins as possible.

Equation 6. CBOOT = 100 nF

As a general rule, the local VGVDD bypass capacitor must be 10 times greater than the value of CBOOT, as shown in Equation 7.

Equation 7. CGVDD = 1 µF

The bootstrap and bias capacitors must be ceramic types with X7R dielectric. The voltage rating must be twice that of the maximum VGVDD considering capacitance tolerances once the devices have a DC bias voltage across them and to ensure long-term reliability.