JAJSN04A april   2023  – august 2023 LM2103

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select External Bootstrap Diode and Its Series Resistor
        2. 8.2.2.2 Select Bootstrap and GVDD Capacitor
        3. 8.2.2.3 Select External Gate Driver Resistor
        4. 8.2.2.4 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20230217-SS0I-HGK5-BJTG-S82SWMBJQCSM-low.svg Figure 5-1 D Package, 8-Pin SOIC (Top View)
Table 5-1 Pin Functions
PIN DESCRIPTION
NO. NAME TYPE(1)
1

GVDD

 P Gate driver positive supply rail. Locally decouple to ground using low ESR and ESL capacitor located as close to IC as possible.
2

INH

 I High-side control input. The INH input is compatible with TTL and CMOS input thresholds. Unused INH input must be tied to ground and not left open.
3 INL I Low-side control input. The inverting INL input is compatible with TTL and CMOS input thresholds. Unused INL input must be tied to GVDD and not left open.
4

GND

 G Ground. All signals are referenced to this ground.
5 GL O Low-side gate driver output. Connect to the gate of the low-side MOSFET or one end of external gate resistor, when used.
6 SH P High-side source connection. Connect to the negative terminal of the bootstrap capacitor and to the source of the high-side MOSFET.
7 GH O High-side gate driver output. Connect to the gate of the high-side MOSFET or one end of external gate resistor, when used.
8 BST P High-side gate driver positive supply rail. Connect the positive terminal of the bootstrap capacitor to BST and the negative terminal of the bootstrap capacitor to SH. The bootstrap capacitor must be placed as close to IC as possible.
(1) G = Ground, I = Input, O = Output, and P = Power