JAJSN04A april   2023  – august 2023 LM2103

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Start-Up and UVLO
      2. 7.3.2 Input Stages
      3. 7.3.3 Level Shift
      4. 7.3.4 Output Stages
      5. 7.3.5 SH Transient Voltages Below Ground
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select External Bootstrap Diode and Its Series Resistor
        2. 8.2.2.2 Select Bootstrap and GVDD Capacitor
        3. 8.2.2.3 Select External Gate Driver Resistor
        4. 8.2.2.4 Estimate the Driver Power Loss
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3 Application Curves

Figure 8-2 and Figure 8-3 show the fall times and turn-off propagation delays for the low side driver and the high side driver respectively. Likewise, Figure 8-4 and Figure 8-5 show the fall times and turn-off propagation delays, and Figure 8-6 and Figure 8-7 show the propagation delays with deadtime. Each channel (INH, INL, GH, and GL) is labeled and displayed on the left hand of the waveforms.

The testing condition: load capacitance is 1 nF, gate resistor is 4Ω, VDD = 12 V, fSW = 50 kHz.

GUID-20230807-SS0I-8WGR-B01R-5FLGZ09DPPCC-low.svg
CL = 1 nF RG = 4Ω VDD = 12 V fSW = 50 kHz
Figure 8-2 GL Fall Time and INL to GL Turn-off Propagation Delay
GUID-20230807-SS0I-5FRT-DS1M-4XTRCMHLSFZR-low.svg
CL = 1 nF RG = 4Ω VDD = 12 V fSW = 50 kHz
Figure 8-4 GL Rise Time and INL to GL Turn-on Propagation Delay
GUID-20230807-SS0I-397L-SM84-LCBTGVNZDHPK-low.svg
CL = 1 nF RG = 4Ω VDD = 12 V fSW = 50 kHz
Figure 8-6 GL Turn-on Propagation Delay with Deadtime
GUID-20230807-SS0I-G7RD-G4QZ-T3CJMD5ZXWBX-low.svg
CL = 1 nF RG = 4Ω VDD = 12 V fSW = 50 kHz
Figure 8-3 GH Fall Time and INH to GH Turn-off Propagation Delay
GUID-20230807-SS0I-ZNMJ-NSD4-5RQMNS6ST4XT-low.svg
CL = 1 nF RG = 4Ω VDD = 12 V fSW = 50 kHz
Figure 8-5 GH Rise Time and INH to GH Turn-on Propagation Delay
GUID-20230807-SS0I-R1JP-W2KN-XN9PCW8J3NX4-low.svg
CL = 1 nF RG = 4Ω VDD = 12 V fSW = 50 kHz
Figure 8-7 GH Turn-on Propagation Delay with Deadtime