SNVS859C July   2012  – September 2016 LM25101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Start-Up and UVLO
      2. 8.3.2 Level Shift
      3. 8.3.3 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting External Gate Driver Resistor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM25101 is a high voltage gate driver designed to drive both the high-side and low-side N-Channel MOSFETs in a half or full bridge configuration or in a synchronous buck circuit. The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel MOSFETs control in half-bridge, full-bridge, push-pull, two switch forward, and active clamp topologies. The outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing full and independent flexibility to control the state (ON and OFF) of the output.

9.2 Typical Application

LM25101 application_SNVS859.gif Figure 21. Application Diagram

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 5 as the input parameters.

Table 5. Design Parameters

PARAMETER EXAMPLE VALUE
Gate driver LM25101 (C version)
MOSFET CSD19534KCS
VDD 10 V
QG 17 nC
fSW 500 kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Selecting External Gate Driver Resistor

External gate driver resistor (RGATE) is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the current coming out of the gate driver.

Peak HO pullup current is calculated using Equation 1.

Equation 1. LM25101 Equation.gif

where

  • IOHHis the peak pullup current
  • VDHis the bootstrap diode forward voltage drop
  • RHOHis the gate driver internal HO pullup resistance (1)
  • RGateis the external gate drive resistance
  • R(GFET_Int) is the MOSFET internal gate resistance, provided by the transistor data sheet
(1)
(1)This value is either provided directly by the data sheet or is estimated from the testing conditions using RHOH = VOHH / IHO.

Similarly, Peak HO pulldown current is calculated using Equation 2.

Equation 2. LM25101 eq06_snvsag6.gif

where

  • RHOL is the HO pulldown resistance

Peak LO pullup current is calculated using Equation 3.

Equation 3. LM25101 eq07_snvsag6.gif

where

  • RLOH is the LO pullup resistance

Peak LO pulldown current is calculated using Equation 4.

Equation 4. LM25101 eq08_snvsag6.gif

where

  • RLOL is the LO pulldown resistance

If the application requires fast turnoff, an anti-paralleled diode on RGate may be used to bypass the external gate drive resistor and speed up the turnoff transition.

9.2.3 Application Curves

Figure 22 and Figure 23 show the rising and falling time and turnon and turnoff propagation delay testing waveform at room temperature. Each channel (HI, LI, HO, LO) is labeled and displayed on the left hand of the waveform.

The HI and LI pins are shorted together for these test waveforms. Therefore, the propagation delay matching between the channels can be measured and inspected.

LM25101 wvfm01_rising_time_turn_on_snvsag6.gif
CL = 1 nF VDD = 12 V fSW = 500 kHz
Figure 22. Rising Time and Turnon Propagation Delay
LM25101 wvfm02_falling_time_turn_off_snvsag6.gif
CL = 1 nF VDD = 12 V fSW = 500 kHz
Figure 23. Falling Time and Turnoff Propagation Delay