JAJSDG8F July   2011  – March 2018 LM25118

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     概略回路図
  3. 3 概要
    1.     効率とVINおよびIOUTとの関係、VOUT = 12V
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO
      2. 7.3.2 Oscillator and Sync Capability
      3. 7.3.3 Error Amplifier and PWM Comparator
      4. 7.3.4 Ramp Generator
      5. 7.3.5 Current Limit
      6. 7.3.6 Maximum Duty Cycle
      7. 7.3.7 Soft Start
      8. 7.3.8 HO Output
      9. 7.3.9 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buck Mode Operation: VIN > VOUT
      2. 7.4.2 Buck-Boost Mode Operation: VIN ≊ VOUT
      3. 7.4.3 High Voltage Start-Up Regulator
      4. 7.4.4 Enable
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  R7 = RT
        3. 8.2.2.3  Inductor Selection – L1
        4. 8.2.2.4  R13 = RSENSE
        5. 8.2.2.5  C15 = CRAMP
        6. 8.2.2.6  Inductor Current Limit Calculation
        7. 8.2.2.7  C9 - C12 = Output Capacitors
        8. 8.2.2.8  D1
        9. 8.2.2.9  D4
        10. 8.2.2.10 C1 – C5 = Input Capacitors
        11. 8.2.2.11 C20
        12. 8.2.2.12 C8
        13. 8.2.2.13 C16 = CSS
        14. 8.2.2.14 R8, R9
        15. 8.2.2.15 R1, R3, C21
        16. 8.2.2.16 R2
        17. 8.2.2.17 Snubber
        18. 8.2.2.18 Error Amplifier Configuration
          1. 8.2.2.18.1 R4, C18, C17
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bias Power Dissipation Reduction
    2. 9.2 Thermal Considerations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Layout Guidelines

In a buck-boost regulator, there are two loops where currents are switched very fast. The first loop starts from the input capacitors, and then to the buck switch, the inductor, the boost switch then back to the input capacitor. The second loop starts from the inductor, and then to the output diode, the output capacitor, the recirculating diode, and back to the inductor. Minimizing the PCB area of these two loops reduces the stray inductance and minimizes noise and the possibility of erratic operation. A ground plane in the PCB is recommended as a means to connect the input filter capacitors to the output filter capacitors and the PGND pins of the LM25118. Connect all of the low current ground connections (CSS, RT, CRAMP) directly to the regulator AGND pin. Connect the AGND and PGND pins together through topside copper area covering the entire underside of the device. Place several vias in this underside copper area to the ground plane of the input capacitors.