JAJSCZ3A March   2017  – February 2018 LM25141-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-Up Regulator
      2. 8.3.2  VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  Synchronization
      5. 8.3.5  Frequency Dithering (Spread Spectrum)
      6. 8.3.6  Enable
      7. 8.3.7  Power Good
      8. 8.3.8  Output Voltage
        1. 8.3.8.1 Minimum Output Voltage Adjustment
      9. 8.3.9  Current Sense
      10. 8.3.10 DCR Current Sensing
      11. 8.3.11 Error Amplifier and PWM Comparator
      12. 8.3.12 Slope Compensation
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 Standby Mode
      15. 8.3.15 Soft Start
      16. 8.3.16 Diode Emulation
      17. 8.3.17 High- and Low-Side Drivers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Inductor Calculation
        3. 9.2.2.3 Current Sense Resistor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Input Filter
          1. 9.2.2.5.1 EMI Filter Design
          2. 9.2.2.5.2 MOSFET Selection
          3. 9.2.2.5.3 Driver Slew Rate Control
          4. 9.2.2.5.4 Frequency Dithering
        6. 9.2.2.6 Control Loop
          1. 9.2.2.6.1 Feedback Compensator
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Procedure
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
        1. 12.2.1.1 PCBレイアウトについてのリソース
        2. 12.2.1.2 熱設計についてのリソース
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.5.2 MOSFET Selection

The LM25141-Q1 gate drivers are powered by the internal 5-V VCC bias regulator. To reduce power dissipation in the controller and improve efficiency, the VCCX pin should be connected to the 5-V output or an external 5-V bias supply. The MOSFETs used with the LM25141-Q1 require a logic-level gate threshold with RDS(ON) specified with VGS = 4.5 V or lower.

The MOSFETs must be chosen with a VDS rating to withstand the maximum VIN voltage plus supply voltage transients and spikes (ringing). For automotive applications, the maximum VIN occurs during a load dump and the voltage can surge up to 42 V under some conditions. A MOSFET with a VDS rating of 60 V would meet most application requirements. The N-channel MOSFETs must be capable of delivering the load current plus peak ripple current during switching.

The high-side MOSFET losses are associated with the RDS(ON) of the MOSFET and the switching losses.

Equation 45. LM25141-Q1 equation_44_snvsaj6.gif
Equation 46. LM25141-Q1 equation_45_snvsaj6.gif

where

  • tr = ts = 17 ns

The losses in the low side MOSFET include: RDS(ON) losses, dead time losses, and losses in the MOSFETs internal body diode. The body diode conducts the inductor current during the dead time before the rising edge of the switch node; minority carriers are injected into and stored in the diode PN junction when forward biased. As the high-side FET starts to turnon, a negative current must first flow through the diode to remove the stored charge before the diode can block a reverse voltage. During this time, the high side drain-source voltage remains at VIN until all the diode minority carriers are removed. Then, the diode begins to block negative voltage and the reverse current continues to flow to charge the body diode depletion capacitance. The total charge involved in this period is called reverse-recovery charge Qrr.

Equation 47. LM25141-Q1 equation_46_snvsaj6.gif
Equation 48. LM25141-Q1 equation_47_snvsaj6.gif

where

  • tdr and tdf are the switch node voltage rise and fall times (20 ns)
  • VD(FET) is the forward voltage drop across the low-side MOSFET internal body diode (0.8 V)
  • DQrr is the internal body diode reverse recovery charge (105 nC)
  • RDS(ON) is the on resistance of the MOSFETs (26 mΩ at TJ = 125°C)

Table 4 provides parameters for several MOSFETs that have tested in the LM25141-Q1 evaluation module.

Table 4. EVM MOSFETs

MANUFACTURER PART NUMBER VDS (V) ID (A) Qg(MAX) (nC)
VGS = 4.5 V		 RDS(ON) (mΩ)
VGS = 4.5 V 		COSS(MAX) (pF) APPLICATION
VISHAY SQJ850EP 60 24 30 32 215 Automotive high power
VISHAY SQ7414EN 60 5.6 25 36 175 Automotive low power
Texas Instruments CSD18534Q5A 60 13 11.1 12.4 217 Industrial