JAJSCZ3A March   2017  – February 2018 LM25141-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High Voltage Start-Up Regulator
      2. 8.3.2  VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  Synchronization
      5. 8.3.5  Frequency Dithering (Spread Spectrum)
      6. 8.3.6  Enable
      7. 8.3.7  Power Good
      8. 8.3.8  Output Voltage
        1. 8.3.8.1 Minimum Output Voltage Adjustment
      9. 8.3.9  Current Sense
      10. 8.3.10 DCR Current Sensing
      11. 8.3.11 Error Amplifier and PWM Comparator
      12. 8.3.12 Slope Compensation
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 Standby Mode
      15. 8.3.15 Soft Start
      16. 8.3.16 Diode Emulation
      17. 8.3.17 High- and Low-Side Drivers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Inductor Calculation
        3. 9.2.2.3 Current Sense Resistor
        4. 9.2.2.4 Output Capacitor
        5. 9.2.2.5 Input Filter
          1. 9.2.2.5.1 EMI Filter Design
          2. 9.2.2.5.2 MOSFET Selection
          3. 9.2.2.5.3 Driver Slew Rate Control
          4. 9.2.2.5.4 Frequency Dithering
        6. 9.2.2.6 Control Loop
          1. 9.2.2.6.1 Feedback Compensator
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Layout Procedure
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 開発サポート
        1. 12.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
        1. 12.2.1.1 PCBレイアウトについてのリソース
        2. 12.2.1.2 熱設計についてのリソース
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 DEMB I Diode Emulation pin. Connect the DEMB pin to AGND to enable diode emulation. If it is connected to VDDA, the LM25141-Q1 operates in Forced PWM (FPWM) mode with continuous conduction at light loads. The DEMB pin can also be used as a synchronization input to synchronize the internal oscillator to an external clock.
2 VDDA P Internal analog bias regulator output. Connect a capacitor from the VDDA pin to AGND.
3 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
4 RT I A resistor from the RT pin to ground shifts the oscillator frequency up or down from 2.2 MHz (1.8 MHz to 2.53 MHz), or 440 kHz (300 kHz to 500 kHz). An analog voltage can be applied to the RT pin (through a resistor) to shift the oscillator frequency.
5 DITH O A capacitor connected between the DITH pin and AGND is charged and discharged with a 20-µA current source. If Dither is enabled, the voltage on the DITH pin ramps up and down, modulating the oscillator frequency between –5% and +5% of the internal oscillator. Connecting DITH to VDDA disables the dithering feature. DITH is ignored if an external synchronization clock is used.
6 OSC I Frequency selection pin. Connecting the OSC pin to VDDA sets the oscillator frequency to 2.2 MHz. Connecting the OSC pin to AGND sets the frequency to 440 kHz.
7 LOL O Low-side gate driver turnoff output.
8 LO O Low-side gate driver turnon output.
9 PGND G Power ground connection pin for low-side NMOS gate driver.
10 VCC P VCC bias supply pin. Connect a capacitor from the VCC pin to PGND.
11 HB P High-side driver supply for bootstrap gate drive.
12 SW Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
13 HO O High-side gate driver turnon output.
14 HOL O High-side gate driver turnoff output.
15 VIN P Supply voltage input source for the VCC regulator
16 VCCX P Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to the VCC pin and the internal VCC regulator is disabled. If VCCX is unused, it must be grounded.
17 VOUT I Current sense amplifier input. Connect this pin to the output side of the current sense resistor.
18 CS I Current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
19 FB I Connect the FB pin to VDDA for a fixed 3.3-V output or connect FB to AGND for a fixed 5-V output. Connecting the FB pin to the appropriate output divider network sets the output voltage between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V.
20 COMP I Output of the transconductance error amplifier.
21 PG O An open-collector output which switches low if VOUT is outside of the power good window.
22 SS I Soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft start. Pulling SS pin below 80 mV turns off the gate driver outputs, but all the other functions remain active.
23 EN I An active high logic input enables the controller.
24 RES O Restart timer pin. An external capacitor configures the hiccup mode current limiting. The capacitor at the RES pin determines the time the controller will remain off before automatically restarting in hiccup mode. The hiccup mode commences when the controller experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connecting the RES pin to VDD during power up disables hiccup mode protection.