Figure 9-37 shows a single-sided layout of a synchronous buck regulator with discrete power MOSFETs, Q1 and Q2, in SON 5-mm × 6-mm case size. The power stage is surrounded by a GND pad geometry to connect an EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.

The high-frequency power loop current flows through MOSFETs Q1 and Q2, through the power ground plane on layer 2, and back to VIN through the 0402 ceramic capacitors C17 through C22. The currents flowing in opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance. Figure 9-39 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in Figure 9-38, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of Q2.

Six 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain of Q1. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic loop inductance.

Figure 9-37 PCB Top Layer – High Density, Single-sided Design

Additional guidelines to improve noise immunity and reduce EMI are as follows:

• Make the ground connections to the LM25149-Q1 controller as shown in Figure 9-37. Create a power ground directly connected to all high-power components and an analog ground plane for sensitive analog components. The analog ground plane for AGND and power ground plane for PGND must be connected at a single point directly under the IC – at the die attach pad (DAP).
• Connect the MOSFETs (switch node) directly to the inductor terminal with short copper connections (without vias) as this net has high dv/dt and contributes to radiated EMI. The single-layer routing of the switch-node connection means that switch-node vias with high dv/dt do not appear on the bottom side of the PCB. This avoids e-field coupling to the reference ground plane during the EMI test. VIN and PGND plane copper pours shield the polygon connecting the MOSFETs to the inductor terminal, further reducing the radiated EMI signature.
• Place the EMI filter components on the bottom side of the PCB so that they are shielded from the power stage components on the top side.

Figure 9-38 Layer 2 Full Ground Plane Directly Under the Power Components

Figure 9-39 PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing ⁽¹⁾