To configure for dual-phase operation, two controllers are required. The LM25149-Q1 can only be configured in a single or dual-phase configuration where both outputs are tied together. Additional phases cannot be added. Refer to Figure 8-8. Configure the first controller (CNTRL1) as a primary controller and the second controller (CNTRL2) as a secondary. To configure CNTRL1 as a primary controller, install a 54-kΩ or a 71.5-kΩ resistor from CNFG to AGND. To configure the CNTRL2 as a secondary controller, install a 90.9-kΩ resistor from CNFG to AGND. This disables the error amplifier of CNTRL2, placing it into a high-impedance state. Connect the EXTCOMP pins of the primary and secondary controllers together. The internal compensation amplifier feature is not supported when the controller is in dual-phase mode.

In dual-phase mode, the PG/SYNC pin of the primary controller becomes a SYNCOUT. Refer to the Electrical Characteristics for voltage levels. Connect PG of the primary to PFM/SYNC (SYNCIN) of the secondary controller. The PG/SYNCOUT signal of the primary controller is 180° out-of-phase and facilitates interleaved operation. RT is not used for the oscillator when the LM25149-Q1 is in secondary controller mode, but instead is used for slope compensation. Therefore, select the RT resistance to be the same as that of the primary controller. The oscillator is derived from the primary controller. When in primary/secondary mode, enable both controllers simultaneously for start-up. After the regulator has started, pull the secondary EN pin low (< 0.8 V) for phase shedding if needed at light load to increase the efficiency.

Configure PFM mode by connecting the PFM/SYNC of the primary to VDDA and the FB of the secondary to VDDA as shown in Figure 8-8. Configure FPWM mode by connecting PFM/SYNC of the primary and FB of the secondary both to AGND. An external synchronization signal can be applied to the primary PFM/SYNC (SYNCIN), and the secondary FB must be configured for FPWM. If an external SYNCIN signal is applied after start-up while in primary/secondary mode, there is a two-clock cycle delay before the LM25149-Q1 locks on to the external synchronization signal.

PFM pulse skipping is used to reduce the I_Q current and the light-load efficiency. When this occurs, the primary controller disables its synchronization clock output, so phase shedding is not supported. Phase shedding is supported in FPWM only. In FPWM, enable or disable the secondary controller as needed to support higher load current or better light-load efficiency, respectively. When the secondary is disabled and then re-enabled, its internal soft-start is pulled low and the LM25149-Q1 goes through a normal soft-start sequence.

When the LM25149-Q1 is configured for a single-output dual-phase operation using the internal 3.3-V feedback resistor divider, the internal bootstrap UV circuit can source current out of the SW pin, charging up the output capacitors approximately to 3.6 V. If this behavior is undesirable, the user can add a 100-kΩ resistor from VOUT to GND to bleed off the charge on the output capacitors.

For more information, see Benefits of a Multiphase Buck Converter technical brief and Multiphase Buck Design From Start to Finish application report.