JAJSIW4A April   2020  – September 2020 LM25183

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Integrated Power MOSFET
      2. 7.3.2  PSR Flyback Modes of Operation
      3. 7.3.3  Setting the Output Voltage
        1. 7.3.3.1 Diode Thermal Compensation
      4. 7.3.4  Control Loop Error Amplifier
      5. 7.3.5  Precision Enable
      6. 7.3.6  Configurable Soft Start
      7. 7.3.7  External Bias Supply
      8. 7.3.8  Minimum On-Time and Off-Time
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Wide VIN, Low IQ PSR Flyback Converter Rated at 12 V, 0.6 A
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3  Flyback Transformer – T1
          4. 8.2.1.2.4  Flyback Diode – DFLY
          5. 8.2.1.2.5  Leakgae Inductance Clamp Circuit – DF, DCLAMP
          6. 8.2.1.2.6  Output Capacitor – COUT
          7. 8.2.1.2.7  Input Capacitor – CIN
          8. 8.2.1.2.8  Feedback Resistor – RFB
          9. 8.2.1.2.9  Thermal Compensation Resistor – RTC
          10. 8.2.1.2.10 UVLO Resistors – RUV1, RUV2
          11. 8.2.1.2.11 Soft-Start Capacitor – CSS
          12.        50
      2. 8.2.2 Application Curves
      3. 8.2.3 Design 2: PSR Flyback Converter With Dual Outputs of 15 V and –15 V at 0.3 A
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Flyback Transformer – T1
          2. 8.2.3.2.2 Flyback Diodes – DFLY1 and DFLY2
          3. 8.2.3.2.3 Input Capacitor – CIN
          4. 8.2.3.2.4 Output Capacitors – COUT1, COUT2
          5. 8.2.3.2.5 Feedback Resistor – RFB
          6. 8.2.3.2.6 Thermal Compensation Resistor – RTC
          7. 8.2.3.2.7 Output Voltage Clamp Zeners – DOUT1 and DOUT2
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

7.4.2 Standby Mode

The internal bias rail LDO regulator has a lower enable threshold than the converter itself. When VEN/UVLO is above 0.6 V and below the precision-enable threshold (1.5 V typically), the internal LDO is on and regulating. The precision enable circuitry is turned on once the internal VCC is above its UV threshold. The switching action and voltage regulation are not enabled until VEN/UVLO rises above the precision enable threshold.