JAJSEF9 December   2017 LM25575-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      簡略化されたアプリケーション回路図
  4. 4 改訂履歴
  5. 5  Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Voltage Start-Up Regulator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown and Stand-by Mode
      2. 7.4.2 Error Amplifier and PWM Comparator
      3. 7.4.3 Ramp Generator
      4. 7.4.4 Maximum Duty Cycle and Input Drop-out Voltage
      5. 7.4.5 Current Limit
      6. 7.4.6 Soft-Start
      7. 7.4.7 Boost Pin
      8. 7.4.8 Thermal Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  External Components
      2. 8.1.2  R3 (RT)
      3. 8.1.3  L1
      4. 8.1.4  C3 (CRAMP)
      5. 8.1.5  C9, C10
      6. 8.1.6  D1
      7. 8.1.7  C1, C2
      8. 8.1.8  C8
      9. 8.1.9  C7
      10. 8.1.10 C4
      11. 8.1.11 R5, R6
      12. 8.1.12 R1, R2, C12
      13. 8.1.13 R7, C11
      14. 8.1.14 R4, C5, C6
      15. 8.1.15 BIas Power Dissipation Reduction
    2. 8.2 Typical Application
      1. 8.2.1 Typical Schematic for High Frequency (1 MHz) Application
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PCB Layout and Thermal Considerations
    2. 9.2 Layout Example
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 開発サポート
        1. 10.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 コミュニティ・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

PWP
16-Pin HTSSOP
Top View
LM25575-Q1 20212102.gif

Pin Functions

NO.NameDescription
1 VCC Output of the bias regulator
VCC tracks VIN up to 9 V. Beyond 9 V, VCC is regulated to 7 Volts. A 0.1 uF to 1 uF ceramic decoupling capacitor is required. An external voltage (7.5 V – 14 V) can be applied to this pin to reduce internal power dissipation.
2 SD Shutdown or UVLO input
If the SD pin voltage is below 0.7 V the regulator will be in a low power state. If the SD pin voltage is between 0.7 V and 1.225 V the regulator will be in standby mode. If the SD pin voltage is above 1.225 V the regulator will be operational. An external voltage divider can be used to set a line undervoltage shutdown threshold. If the SD pin is left open circuit, a 5 µA pull-up current source configures the regulator fully operational.
3 VIN Input supply voltage
Nominal operating range: 6 V to 42 V
4 SYNC Oscillator synchronization input or output
The internal oscillator can be synchronized to an external clock with an external pull-down device. Multiple LM25575-Q1 devices can be synchronized together by connection of their SYNC pins.
5 COMP Output of the internal error amplifier
The loop compensation network should be connected between this pin and the FB pin.
6 FB Feedback signal from the regulated output
This pin is connected to the inverting input of the internal error amplifier. The regulation threshold is 1.225 V.
7 RT Internal oscillator frequency set input
The internal oscillator is set with a single resistor, connected between this pin and the AGND pin.
8 RAMP Ramp control signal
An external capacitor connected between this pin and the AGND pin sets the ramp slope used for current mode control. Recommended capacitor range 50 pF to 2000 pF.
9 AGND Analog ground
Internal reference for the regulator control functions
10 SS Soft-start
An external capacitor and an internal 10 µA current source set the time constant for the rise of the error amp reference. The SS pin is held low during standby, VCC UVLO and thermal shutdown.
11 OUT Output voltage connection
Connect directly to the regulated output voltage.
12 PGND Power ground
Low side reference for the PRE switch and the IS sense resistor.
13 IS Current sense
Current measurement connection for the re-circulating diode. An internal sense resistor and a sample/hold circuit sense the diode current near the conclusion of the off-time. This current measurement provides the DC level of the emulated current ramp.
14 SW Switching node
The source terminal of the internal buck switch. The SW pin should be connected to the external Schottky diode and to the buck inductor.
15 PRE Pre-charge assist for the bootstrap capacitor
This open drain output can be connected to SW pin to aid charging the bootstrap capacitor during very light load conditions or in applications where the output may be pre-charged before the LM25575-Q1 is enabled. An internal pre-charge MOSFET is turned on for 250 ns each cycle just prior to the on-time interval of the buck switch.
16 BST Boost input for bootstrap capacitor
An external capacitor is required between the BST and the SW pins. A 0.022 µF ceramic capacitor is recommended. The capacitor is charged from VCC via an internal diode during the off-time of the buck switch.
NA EP Exposed Pad
Exposed metal pad on the underside of the device. It is recommended to connect this pad to the PWB ground plane, in order to aid in heat dissipation.