LM26480-Q1は車載用認定済みの、低消費電力デジタル・アプリケーション用に最適化された多機能パワー・マネジメント・ユニット(PMU)です。このデバイスは、2つの非常に高効率な1.5A降圧型DC/DCコンバータと、2つの300mAリニア・レギュレータを内蔵しています。DC/DC降圧型コンバータは標準効率が96%で、消費電力を最小限に抑えられます。機能として、ソフトスタート、低電圧誤動作防止、電流過負荷保護、熱過負荷保護、およびBuck1および2の出力電圧レベルを監視する、内蔵のパワー・オン・リセット(POR)回路があります。
型番 | パッケージ | 本体サイズ(公称) |
---|---|---|
LM26480-Q1 | WQFN (24) | 4.00mm×4.00mm |
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Changes from B Revision (December 2016) to C Revision
Changes from A Revision (June 2016) to B Revision
Changes from * Revision (January 2016) to A Revision
ORDER SUFFIX | SPEC | OSCILLATOR FREQUENCY | BUCK MODES | nPOR DELAY | UVLO | SYNC | AECQ |
---|---|---|---|---|---|---|---|
QSQ-AA | NOPB | 2 MHz | Auto-Mode | 60 mS | Enabled | Disabled | Grade 1 |
QSQ-CF | NOPB | 2.1 MHz | Forced PWM | 60 mS | Disabled | Disabled | Grade 1 |
QSQ-8D | NOPB | 2.1 MHz | Forced PWM | 130 µS | Enabled | Disabled | Grade 1 |
POWER BLOCK INPUT | ENABLED | DISABLED | NOTE |
---|---|---|---|
VINLDO12 | VIN+ | VIN+ | Always Powered |
AVDD | VIN+ | VIN+ | Always Powered |
VIN1 | VIN+ | VIN+ or 0V | |
VIN2 | VIN+ | VIN+ or 0V | |
VINLDO1 | ≤ VIN+ | ≤ VIN+ | If Enabled, minimum VIN is 1.74 V |
VINLDO2 | ≤ VIN+ | ≤ VIN+ | If Enabled, minimum VIN is 1.74 V |
PIN | I/O | TYPE(1) | DESCRIPTION | |
---|---|---|---|---|
NO. | NAME | |||
1 | VINLDO12 | I | P | Analog power for internal functions (VREF, BIAS, I2C, Logic) |
2 | SYNC | I | G/(D) | Frequency synchronization pin, which allows the user to connect an external clock signal to synchronize the PMIC internal oscillator. Default OFF and must be grounded when not used. |
3 | NPOR | O | D | nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100-kΩ pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See Flexible Power-On Reset (Power Good with Delay) for more information. |
4 | GND_SW1 | G | G | Buck1 NMOS power ground |
5 | SW1 | O | P | Buck1 switcher output pin |
6 | VIN1 | I | P | Power in from either DC source or battery to Buck1 |
7 | ENSW1 | I | D | Enable pin for Buck1 switcher, a logic HIGH enables Buck1. Pin cannot be left floating. |
8 | FB1 | I | A | Buck1 input feedback terminal |
9 | GND_C | G | G | Non-switching core ground pin |
10 | AVDD | I | P | Analog Power for Buck converters |
11 | FB2 | I | A | Buck2 input feedback terminal |
12 | ENSW2 | I | D | Enable pin for Buck2 switcher, a logic HIGH enables Buck2. Pin cannot be left floating. |
13 | VIN2 | I | P | Power in from either DC source or Battery to Buck2 |
14 | SW2 | O | P | Buck2 switcher output pin |
15 | GND_SW2 | G | G | Buck2 NMOS |
16 | ENLDO2 | I | D | LDO2 enable pin, a logic HIGH enables LDO2. Pin cannot be left floating. |
17 | ENLDO1 | I | D | LDO1 enable pin, a logic HIGH enables LDO1. Pin cannot be left floating. |
18 | GND_L | G | G | LDO ground |
19 | VINLDO1 | I | P | Power in from either DC source or battery to LDO1 |
20 | LDO1 | O | P | LDO1 Output |
21 | FBL1 | I | A | LDO1 feedback terminal |
22 | FBL2 | I | A | LDO2 feedback terminal |
23 | LDO2 | O | P | LDO output |
24 | VINLDO2 | I | P | Power in from either DC source or battery to LDO2. |
DAP | DAP | G | G | Connection is not necessary for electrical performance, but it is recommended for better thermal dissipation. |