JAJSA30G November   2002  – May 2019 LM2733

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      効率と負荷電流との関係
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switching Frequency
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Pin Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the External Capacitors
        2. 8.2.2.2  Selecting the Output Capacitor
        3. 8.2.2.3  Selecting the Input Capacitor
        4. 8.2.2.4  Feedforward Compensation
        5. 8.2.2.5  Selecting Diodes
        6. 8.2.2.6  Setting the Output Voltage
        7. 8.2.2.7  Switching Frequency
        8. 8.2.2.8  Duty Cycle
        9. 8.2.2.9  Inductance Value
        10. 8.2.2.10 Maximum Switch Current
        11. 8.2.2.11 Calculating Load Current
        12. 8.2.2.12 Design Parameters VSW and ISW
        13. 8.2.2.13 Thermal Considerations
        14. 8.2.2.14 Minimum Inductance
        15. 8.2.2.15 Inductor Suppliers
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 商標
    2. 11.2 静電気放電に関する注意事項
    3. 11.3 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The LM2733 device is a switching converter IC that operates at a fixed frequency (0.6 or 1.6 MHz) using current-mode control for fast transient response over a wide input voltage range and incorporate pulse-by-pulse current limiting protection. Because this is current mode control, a 50 mΩ sense resistor in series with the switch FET is used to provide a voltage (which is proportional to the FET current) to both the input of the pulse width modulation (PWM) comparator and the current limit amplifier.

At the beginning of each cycle, the S-R latch turns on the FET. As the current through the FET increases, a voltage (proportional to this current) is summed with the ramp coming from the ramp generator and then fed into the input of the PWM comparator. When this voltage exceeds the voltage on the other input (coming from the Gm amplifier), the latch resets and turns the FET off. Since the signal coming from the Gm amplifier is derived from the feedback (which samples the voltage at the output), the action of the PWM comparator constantly sets the correct peak current through the FET to keep the output volatge in regulation.

Q1 and Q2 along with R3 - R6 form a bandgap voltage reference used by the IC to hold the output in regulation. The currents flowing through Q1 and Q2 will be equal, and the feedback loop will adjust the regulated output to maintain this. Because of this, the regulated output is always maintained at a voltage level equal to the voltage at the FB node "multiplied up" by the ratio of the output resistive divider.

The current limit comparator feeds directly into the flip-flop, that drives the switch FET. If the FET current reaches the limit threshold, the FET is turned off and the cycle terminated until the next clock pulse. The current limit input terminates the pulse regardless of the status of the output of the PWM comparator.