SLCS007K September   1973  – March 2017 LM111 , LM211 , LM311

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information (8-Pin Packages)
    5. 6.5 Thermal Information (20-Pin Package)
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Voltage Comparison
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Voltage Range
        2. 9.2.2.2 Minimum Overdrive Voltage
        3. 9.2.2.3 Output and Drive Current
        4. 9.2.2.4 Response Time
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • P|8
  • PS|8
  • PW|8
サーマルパッド・メカニカル・データ
発注情報

7 Parameter Measurement Information

LM111 LM211 LM311 tc3_lcs007_1.gif Figure 9. Collector Output Transfer Characteristic Test Circuit
LM111 LM211 LM311 tc6_lcs007.gif Figure 11. Test Circuit for Figure 3 and Figure 4
LM111 LM211 LM311 tc3_lcs007_2.gif Figure 10. Emitter Output Transfer Characteristic Test Circuit
LM111 LM211 LM311 tc9_lcs007.gif Figure 12. Test Circuit for Figure 14 and Figure 15