SNVS796D August   2011  – October 2015 LM3556

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Amplifier Synchronization (TX)
      2. 7.3.2 Input Voltage Flash Monitor (IVFM)
      3. 7.3.3 Fault Protections
        1. 7.3.3.1 Fault Operation
        2. 7.3.3.2 Flash Time-Out
        3. 7.3.3.3 Overvoltage Protection (OVP)
        4. 7.3.3.4 Current Limit
        5. 7.3.3.5 NTC Thermistor Input (TEMP)
        6. 7.3.3.6 Undervoltage Lockout (UVLO)
        7. 7.3.3.7 Thermal Shutdown (TSD)
        8. 7.3.3.8 LED and/or VOUT Fault
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up (Enabling The Device)
      2. 7.4.2 Pass Mode
      3. 7.4.3 Flash Mode
      4. 7.4.4 Torch Mode
      5. 7.4.5 Indicator Mode
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Transferring Data
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  Silicon Revision and Filter Time Register (0x00)
        2. 7.6.1.2  Input Voltage Flash Monitor (IVFM) Mode Register (0x01)
        3. 7.6.1.3  NTC Settings Register (0x02)
        4. 7.6.1.4  Indicator Ramp Time Indicator (0x03)
        5. 7.6.1.5  Indicator Blinking Register (0x04)
        6. 7.6.1.6  Indicator Period Count Register (0x05)
        7. 7.6.1.7  Torch Ramp Time Register (0x06)
        8. 7.6.1.8  Configuration Register (0x07)
        9. 7.6.1.9  Flash Features Register (0x08)
        10. 7.6.1.10 Current Control Register (0x09)
        11. 7.6.1.11 Enable Register (0x0A)
          1. 7.6.1.11.1 Enable Register Mode Bits
          2. 7.6.1.11.2 Control Logic Delays
        12. 7.6.1.12 Flags Register (0x0B)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Capacitor Selection
        2. 8.2.2.2 Input Capacitor Selection
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 NTC Thermistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device And Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, And Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The high switching frequency and large switching currents of the LM3556 make the choice of layout important. The following steps should be used as a reference to ensure the device is stable and maintains proper LED current regulation across its intended operating voltage and current range.

  1. Place CIN on the top layer (same layer as the device), as close as possible to the device. The input capacitor conducts the driver currents during the low-side MOSFET turnon and turnoff and can see current spikes over 1 A in amplitude. Connecting the input capacitor through short, wide traces to both the IN and GND pins reduces the inductive voltage spikes that occur during switching which can corrupt the VIN line.
  2. Place COUT on the top layer (same layer as the device) and as close as possible to the OUT and GND pins. The returns for both CIN and COUT must come together at one point, as close as possible to the GND pin. Connecting COUT through short, wide traces reduces the series inductance on the OUT and GND pins that can corrupt the VOUT and GND lines and cause excessive noise in the device and surrounding circuitry.
  3. Connect the inductor on the top layer close to the SW pin. There must be a low-impedance connection from the inductor to SW due to the large DC inductor current, and at the same time the area occupied by the SW node must be small to reduce the capacitive coupling of the high dV/dt present at SW that can couple into nearby traces.
  4. Logic traces must not be routed near the SW node to avoid any capacitively coupled voltages from SW onto any high-impedance logic lines such as TORCH, STROBE, HWEN, TEMP, SDA, and SCL. A good approach is to insert an inner layer GND plane underneath the SW node and between any nearby routed traces. This creates a shield from the electric field generated at SW.
  5. Terminate the flash LED cathodes directly to the GND pin of the LM3556. If possible, route the LED returns with a dedicated path to keep the high amplitude LED currents out of the GND plane. For flash LEDs that are routed relatively far away from the device, sandwich the forward and return current paths over the top of each other on two layers. This helps reduce the inductance of the LED current paths.

10.2 Layout Example

LM3556 30171807.gif Figure 44. LM3556 Layout Example