SNVS867 June   2014 LM3633

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Bank Mapping
        1. 7.3.1.1 High-Voltage Control Banks (A and B)
        2. 7.3.1.2 Low-Voltage Control Banks (C, D, E, F, G, and H)
      2. 7.3.2 Pattern Generator
      3. 7.3.3 PWM Input
      4. 7.3.4 HWEN Input
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 High-Voltage LED Control
        1. 7.4.1.1  High-Voltage Boost Converter
        2. 7.4.1.2  High-Voltage Current Sinks (HVLED1, HVLED2 and HVLED3)
        3. 7.4.1.3  High-Voltage Current String Biasing
        4. 7.4.1.4  Boost Switching-Frequency Select
        5. 7.4.1.5  Automatic Switching Frequency Shift
        6. 7.4.1.6  Brightness Register Current Control
          1. 7.4.1.6.1 8-Bit Control (Preferred)
          2. 7.4.1.6.2 11-Bit Control
        7. 7.4.1.7  PWM Control
          1. 7.4.1.7.1 PWM Input Frequency Range
          2. 7.4.1.7.2 PWM Input Polarity
          3. 7.4.1.7.3 PWM Zero Detection
        8. 7.4.1.8  Start-up/Shutdown Ramp
        9. 7.4.1.9  Run-Time Ramp
        10. 7.4.1.10 High-Voltage Control A/B Ramp Select
        11. 7.4.1.11 LED Current Mapping Modes
        12. 7.4.1.12 Exponential Mapping
          1. 7.4.1.12.1 8-Bit Code Calculation
          2. 7.4.1.12.2 11-Bit Code Calculation
        13. 7.4.1.13 Linear Mapping
          1. 7.4.1.13.1 8-Bit Code Calculation
          2. 7.4.1.13.2 11-Bit Code Calculation
      2. 7.4.2 Low-Voltage LED Control
        1. 7.4.2.1  Integrated Charge Pump
        2. 7.4.2.2  Charge Pump Disabled
        3. 7.4.2.3  Automatic Gain
        4. 7.4.2.4  Automatic Gain (Flying Capacitor Detection)
        5. 7.4.2.5  1X Gain
        6. 7.4.2.6  2X Gain
        7. 7.4.2.7  Low-Voltage Current Sinks (LVLED1 to LVLED6)
        8. 7.4.2.8  Low-Voltage LED Biasing
        9. 7.4.2.9  Brightness Register Current Control
        10. 7.4.2.10 LED Current Mapping Modes
        11. 7.4.2.11 Exponential Mapping
        12. 7.4.2.12 Linear Mapping
        13. 7.4.2.13 Start-up/Shutdown Ramp
        14. 7.4.2.14 Run-Time Ramp
      3. 7.4.3 Low-Voltage LED Pattern Generator
        1. 7.4.3.1 Delay Time
        2. 7.4.3.2 Rise Time
        3. 7.4.3.3 Fall Time
        4. 7.4.3.4 High Period
        5. 7.4.3.5 Low Period
        6. 7.4.3.6 Low-Level Brightness
        7. 7.4.3.7 High-Level Brightness
      4. 7.4.4 Fault Flags/Protection Features
        1. 7.4.4.1 Open LED String (HVLED)
        2. 7.4.4.2 Shorted LED String (HVLED)
        3. 7.4.4.3 Open LED (LVLED)
        4. 7.4.4.4 Shorted LED (LVLED)
        5. 7.4.4.5 Overvoltage Protection (Inductive Boost)
        6. 7.4.4.6 Current Limit (Inductive Boost)
        7. 7.4.4.7 Current Limit (Charge Pump)
      5. 7.4.5 I2C-Compatible Interface
        1. 7.4.5.1 Start and Stop Conditions
        2. 7.4.5.2 I2C-Compatible Address
        3. 7.4.5.3 Transferring Data
    5. 7.5 Register Descriptions
      1. 7.5.1 Pattern Generator Registers
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Boost Converter Maximum Output Power (Boost)
          1. 8.2.2.1.1 Peak Current Limited
          2. 8.2.2.1.2 Output Voltage Limited
        2. 8.2.2.2 Boost Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Schottky Diode Selection
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Maximum Output Power (Charge Pump)
        7. 8.2.2.7 Charge Pump Flying Capacitor Selection
        8. 8.2.2.8 Charge Pump Output Capacitor Selection
        9. 8.2.2.9 Charge Pump Input Capacitor Selection
      3. 8.2.3 Application Performance Plots
    3. 8.3 Initialization Set Up
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines (Boost)
      1. 10.1.1 Boost Output Capacitor Placement
      2. 10.1.2 Schottky Diode Placement
      3. 10.1.3 Inductor Placement
      4. 10.1.4 Boost Input Capacitor Placement
    2. 10.2 Layout Guidelines (Charge Pump)
      1. 10.2.1 Flying Capacitor (CP) Placement
      2. 10.2.2 Output Capacitor (CPOUT) Placement
      3. 10.2.3 Charge Pump Input Capacitor Placement
    3. 10.3 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines (Boost)

The LM3633 inductive boost converter detects a high switched voltage (up to VOVP) at the SW pin, and a step current (up to ICL_BOOST) through the Schottky diode and output capacitor each switching cycle. The high switching voltage can create interference into nearby nodes due to electric field coupling (I = Cdv/dt). The large step current through the diode and the output capacitor can cause a large voltage spike at the SW pin and the OVP pin due to parasitic inductance in the step current conducting path (V = Ldi/dt). Board layout guidelines are geared towards minimizing this electric field coupling and conducted noise. Figure 73 highlights these two noise-generating components.

30200327.gifFigure 73. LM3633 Inductive Boost Converter Showing Pulsed Voltage at SW (High dv/dt) and Current Through Schottky and COUT (High di/dt)

The following list details the main (layout sensitive) areas of the LM3633 inductive boost converter in order of decreasing importance:

  1. Output Capacitor
    • Schottky Cathode to COUT+
    • COUT− to GND
  2. Schottky Diode
    • SW pin to Schottky Anode
    • Schottky Cathode to COUT+
  3. Inductor
    • SW Node PCB capacitance to other traces
  4. Input Capacitor
    • CIN+ to IN pin

10.1.1 Boost Output Capacitor Placement

Because the output capacitor is in the path of the inductor current discharge path it sees a high-current step from 0 to IPEAK each time the switch turns off and the Schottky diode turns on. Any inductance along this series path from the cathode of the diode through COUT and back into the LM3633 GND pin contributes to voltage spikes (VSPIKE = LP_ × di/dt) at SW and OUT. These spikes can potentially over-voltage the SW pin, or feed through to GND. To avoid this, COUT+ must be connected as close as possible to the Cathode of the Schottky diode, and COUT− must be connected as close as possible to the LM3633 GND bump. The best placement for COUT is on the same layer as the LM3633 so as to avoid any vias that can add excessive series inductance.

10.1.2 Schottky Diode Placement

In the LM3633 boost circuit the Schottky diode is in the path of the inductor current discharge. As a result the Schottky diode sees a high-current step from 0 to IPEAK each time the switch turns off and the diode turns on. Any inductance in series with the diode causes a voltage spike (VSPIKE = LP_ × di/dt) at SW and OUT. This can potentially over-voltage the SW pin, or feed through to VOUT and through the output capacitor and into GND. Connecting the anode of the diode as close as possible to the SW pin and the cathode of the diode as close as possible to COUT+ reduces the inductance (LP_) and minimize these voltage spikes.

10.1.3 Inductor Placement

The node where the inductor connects to the LM3633 SW pin has 2 considerations. First, a large switched voltage (0 to VOUT + VF_SCHOTTKY) appears on this node every switching cycle. This switched voltage can be capacitively coupled into nearby nodes. Second, there is a relatively large current (input current) on the traces connecting the input supply to the inductor and connecting the inductor to the SW pin. Any resistance in this path can cause voltage drops that can negatively affect efficiency and reduce the input operating voltage range.

To reduce the capacitive coupling of the signal on SW into nearby traces, the SW bump-to-inductor connection must be minimized in area. This limits the PCB capacitance from SW to other traces. Additionally, high-impedance nodes that are more susceptible to electric field coupling need to be routed away from SW and not directly adjacent or beneath. This is especially true for traces such as SCL, SDA, HWEN, and PWM. A GND plane placed directly below SW dramatically reduces the capacitance from SW into nearby traces.

Lastly, limit the trace resistance of the VIN-to-inductor connection and from the inductor-to-SW connection, by use of short, wide traces.

10.1.4 Boost Input Capacitor Placement

For the LM3633 boost converter, the input capacitor filters the inductor current ripple, and the internal MOSFET driver currents during turnon of the internal power switch. The driver current requirement can range from 50 mA at 2.7 V to over 200 mA at 5.5 V with fast durations of approximately 10 ns to 20 ns. This appears as high di/dt current pulses coming from the input capacitor each time the switch turns on. Close placement of the input capacitor to the IN pin and to the GND pin is critical since any series inductance between IN and CIN+ or CIN− and GND can create voltage spikes that could appear on the VIN supply line and in the GND plane.

Close placement of the input bypass capacitor at the input side of the inductor is also critical. The source impedance (inductance and resistance) from the input supply, along with the input capacitor of the LM3633, form a series RLC circuit. If the output resistance from the source (RS) is low enough the circuit is underdamped and has a resonant frequency (typically the case). Depending on the size of LS the resonant frequency could occur below, close to, or above the LM3633 switching frequency. This can cause the supply current ripple to be:

  1. Approximately equal to the inductor current ripple when the resonant frequency occurs well above the LM3633 switching frequency;
  2. Greater than the inductor current ripple when the resonant frequency occurs near the switching frequency; or
  3. Less than the inductor current ripple when the resonant frequency occurs well below the switching frequency. Figure 74 shows the series RLC circuit formed from the output impedance of the supply and the input capacitor.

The circuit is redrawn for the AC case where the VIN supply is replaced with a short to GND and the LM3633 + Inductor is replaced with a current source (ΔIL). Equation 1 is the criteria for an underdamped response. Equation 2 is the resonant frequency. Equation 3 is the approximated supply current ripple as a function of LS, RS, and CIN.

As an example, consider a 3.6-V supply with 0.1 Ω of series resistance connected to CIN through 50 nH of connecting traces. This results in an under-damped input-filter circuit with a resonant frequency of 712 kHz. Since both the 1-MHz and 500-kHz switching frequency options lie close to the resonant frequency of the input filter, the supply current ripple is probably larger than the inductor current ripple. In this case, using equation 3, the supply current ripple can be approximated as 1.68 times the inductor current ripple (using a 500 kHz switching frequency) and 0.86 times the inductor current ripple using a 1-MHz switching frequency. Increasing the series inductance (LS) to 500 nH causes the resonant frequency to move to around 225 kHz, and the supply current ripple to be approximately 0.25 times the inductor current ripple (500-kHz switching frequency) and 0.053 times for a 1-MHz switching frequency.

30200328.gifFigure 74. Input RLC Network

10.2 Layout Guidelines (Charge Pump)

The charge pump basically has three areas of concern regarding component placement:

  1. The flying capacitor (CP)
  2. The output capacitor (CPOUT)
  3. The input capacitor

10.2.1 Flying Capacitor (CP) Placement

The charge pump flying capacitor must quickly charge up to the input voltage and then supply the current to the output every switching cycle. Since the charge-pump switching frequency is 1 MHz, the capacitor must be a low-inductance and low-resistive ceramic. Additionally, there must be a low-inductive connection from CP to the LM3633 flying capacitor pin C+ and C−. This is accomplished by placing CP as close as possible to the LM3633 and on the same layer to avoid vias.

10.2.2 Output Capacitor (CPOUT) Placement

The charge pump output capacitor sees the switched charge from the flying capacitor every switching cycle (1 MHz). This fast switching action requires that a low inductive and low resistive capacitor (ceramic) be used and that CPOUT be connected to the LM3633 CPOUT pin with a low inductive connection. This is done by placing CPOUT as close as possible to the CPOUT and GND pins of the LM3633 and on the same layer as the LM3633 to avoid vias.

10.2.3 Charge Pump Input Capacitor Placement

The input capacitor for the LM3633 charge pump is the same one used for the LM3633 inductive boost converter (see Boost Input Capacitor Placement section).

10.3 Layout Example

30200385.gifFigure 75. LM3633 Example Layout