7.3.1 Circuit Operation

During the first portion of each switching cycle, the control block in the LM3671 turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (V_IN – V_OUT)/L, by storing energy in a magnetic field.

During the second portion of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of –V_OUT/L.

The output filter stores charge when the inductor current is high, and releases it when inductor current is low, smoothing the voltage across the load.

The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at the SW pin to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin.

7.3.2 Soft Start

The LM3671 has a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low to logic high after Vin reaches 2.7 V. Soft start is implemented by increasing switch current limit in steps of 70 mA, 140 mA, 280 mA and 1020 mA (typical switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at startup. Typical start-up times with a 10-µF output capacitor and 300-mA load is 400 µs and with 1-mA load is 275 µs.

7.4.1 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This allows the converter to achieve good load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward inversely proportional to the input voltage is introduced.

While in PWM mode, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. At the beginning of each clock cycle the PFET switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator can also turn off the switch in case the current limit of the PFET is exceeded. Then the NFET switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock turning off the NFET and turning on the PFET.

Figure 29. Typical PWM Operation

7.4.2 PFM Operation

At very light load, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency.

The device automatically transitions into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles:

1. The NFET current reaches zero.
2.  The peak PMOS switch current drops below the I_MODE level, (Typically I_MODE < 30 mA + V_IN/42 Ω).

Figure 30. Typical PFM Operation

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between approximately 0.6% and 1.7% above the nominal PWM output voltage. If the output voltage is below the high PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage reaches the high PFM threshold or the peak current exceeds the I_PFM level set for PFM mode. The typical peak current in PFM mode is: I_PFM = 112 mA + V_IN/27 Ω.

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 31), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off, and the device enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is 16 µA (typ.), which allows the device to achieve high efficiency under extremely light load conditions.

If the load current should increase during PFM mode (see Figure 31) causing the output voltage to fall below the low2 PFM threshold, the device will automatically transition into fixed-frequency PWM mode. When V_IN = 2.7 V the device transitions from PWM to PFM mode at approximately 35 mA output current and from PFM to PWM mode at approximately 85 mA , when V_IN = 3.6 V, PWM to PFM transition happens at approximately 50 mA and PFM to PWM transition happens at approximately 100 mA, when V_IN = 4.5 V, PWM to PFM transition happens at approximately 65 mA and PFM to PWM transition happens at approximately 115 mA.

Figure 31. Operation in PFM Mode and Transfer to PWM Mode

7.4.3 Shutdown

Setting the EN input pin low (< 0.4 V) places the LM3671 in shutdown mode. During shutdown the PFET switch, NFET switch, reference, control and bias circuitry of the LM3671 are turned off. Setting EN high (> 1 V) enables normal operation. It is recommended to set EN pin low to turn off the LM3671 during system power up and undervoltage conditions when the supply is less than 2.7 V. Do not leave the EN pin floating.

7.4.4 Low Dropout Operation (LDO)

The LM3671-ADJ can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV.

The minimum input voltage needed to support the output voltage is