SNAS598 Data sheet

SNAS598B July 2012 – July 2015 LM4549B

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PT|48
- MTQF003C

サーマルパッド・メカニカル・データ

発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽⁹⁾

		MIN	MAX	UNIT
Supply Voltage		6	6	V
Input Voltage		−0.3	V_DD +0.3	V
Junction Temperature			150	°C
Soldering Information	Vapor Phase (60 sec.)		215	°C
Soldering Information	Infrared (15 sec.)		220	°C
Storage Temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins except 3	±2000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	Pin 3	±750
		Machine Model (MM)	All pins except 3	±200
		Machine Model (MM)	Pin 3	±100

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
Temperature T_MIN ≤ T_A ≤ T_MAX⁽²⁾	−40	85	°C
Analog Supply	4.2	5.5	V
Digital Supply	3	5.5	V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM4549B	UNIT
		PT (LQFP)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	74	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

The following specifications apply for AV_DD = 5 V, DV_DD = 3.3 V, Fs = 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T_A= 25°C. The reference for 0 dB is 1 Vrms unless otherwise specified.⁽¹⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP⁽⁴⁾	MAX⁽⁵⁾	UNIT
AV_DD	Analog Supply		4.2		5.5	V
DV_DD	Digital Supply		3		5.5	V
D_IDD	Digital Quiescent Power Supply Current	DV_DD = 5 V		34		mA
D_IDD	Digital Quiescent Power Supply Current	DV_DD = 3.3 V		19		mA
A_IDD	Analog Quiescent Power Supply Current	AV_DD = 5.5 V		53		mA
I_DSD	Digital Shutdown Current	PR543210 = 111111		19		µA
I_ASD	Analog Shutdown Current	PR543210 = 111111		70		µA
V_REF	Reference Voltage	No pullup resistor		2.16		V
PSRR	Power Supply Rejection Ratio			40		dB
ANALOG LOOPTHROUGH MODE⁽⁶⁾
	Dynamic⁽⁷⁾	CD Input to Line Output, -60 dB Input THD+N	90	97		dB
THD	Total Harmonic Distortion	V_O= -3 dB, f = 1 kHz, R_L = 10 kΩ		0.013%	0.02%
ANALOG INPUT SECTION
V_IN	Line Input Voltage	LINE_IN, AUX, CD, VIDEO, PC_BEEP, PHONE		1		Vrms
V_IN	Mic Input with 20 dB Gain			0.1		Vrms
V_IN	Mic Input with 0 dB Gain			1		Vrms
Xtalk	Crosstalk	CD Left to Right		-95		dB
Z_IN	Input Impedance⁽⁷⁾	All Analog Inputs	10	40		kΩ
C_IN	Input Capacitance⁽⁷⁾			3.7	7	pF
	Interchannel Gain Mismatch	CD Left to Right		0.1		dB
RECORD GAIN AMPLIFIER - ADC
A_S	Step Size	0 dB to 22.5 dB		1.5		dB
A_M	Mute Attenuation⁽⁷⁾			86		dB
MIXER SECTION
A_S	Step Size	+12 dB to -34.5 dB		1.5		dB
A_M	Mute Attenuation			86		dB
ANALOG TO DIGITAL CONVERTERS
	Resolution			18		Bits
	Dynamic⁽⁷⁾	-60 dB Input THD+N, A-Weighted	86	90		dB
	Frequency Response	-1 dB Bandwidth		20		kHz
DIGITAL TO ANALOG CONVERTERS
	Resolution			18		Bits
	Dynamic⁽⁷⁾	-60 dB Input THD+N, A-Weighted	82	89		dB
THD	Total Harmonic Distortion	V_IN = -3 dB, f = 1 kHz, R_L = 10 kΩ		0.01%
	Frequency Response			20 - 21		kHz
	Group Delay⁽⁷⁾	Sample Frequency = 48 kHz		0.36	1	ms
	Out of Band Energy⁽⁸⁾			-40		dB
	Stop Band Rejection			70		dB
D_T	Discrete Tones			-96		dB
ANALOG OUTPUT SECTION
A_S	Step Size	0 dB to -46.5 dB		1.5		dB
A_M	Mute Attenuation			86		dB
Z_OUT	Output Impedance⁽⁷⁾	All Analog Outputs		220		Ω
DIGITAL I/O⁽⁷⁾
V_IH	High level input voltage		0.65 x DV_DD			V
V_IL	Low level input voltage				0.35 x DV_DD	V
V_OH	High level output voltage	I_O = 2.5 mA	0.90 x DV_DD			V
V_OL	Low level output voltage	I_O = 2.5 mA			0.10 x DV_DD	V
I_L	Input Leakage Current	AC Link inputs			±10	µA
I_L	Tri state Leakage Current	High impedance AC Link outputs			±10	µA
C_IN	AC-Link I/O capacitance⁽⁷⁾	SDout, BitClk, SDin, Sync, Reset# only		4	7.5	pF
I_DR	Output drive current	AC Link outputs		5		mA

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance.

(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX, R_θJA, and the ambient temperature T_A. The maximum allowable power dissipation is P_DMAX = (T_JMAX– T_A)/R_θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4549B, T_JMAX = 150°C. The typical junction-to-ambient thermal resistance is 74°C/W for package number PT0048A.

(3) All voltages are measured with respect to the ground pin, unless otherwise specified.

(4) Typicals are measured at 25°C and represent the parametric norm.

(5) Limits are specified to AOQL (Average Outgoing Quality Level).

(6) Loopthrough mode describes a path from an analog input through the analog mixer to an analog output

(7) These specifications are ensured by design and characterization; they are not production tested.

(8) Out of band energy is measured from 28.8 kHz to 100 kHz relative to a 1-Vrms DAC output.

(9) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

7.6 Timing Requirements

			MIN	NOM	MAX	UNIT
F_BC	BIT_CLK frequency			12.288		MHz
T_BCP	BIT_CLK period			81.4		ns
T_CH	BIT_CLK high	Variation of BIT_CLK duty cycle from 50%			±20%
F_SYNC	SYNC frequency			48		kHz
T_SP	SYNC period			20.8		µs
T_SH	SYNC high pulse width			1.3		µs
T_SL	SYNC low pulse width			19.5		µs
T_DSETUP	Setup Time for codec data input	SDATA_OUT to falling edge of BIT_CLK	10	3.5		ns
T_DHOLD	Hold Time for codec data input⁽¹⁾	Hold time of SDATA_OUT from falling edge of BIT_CLK	10	5.3		ns
T_SSETUP	Setup Time for codec SYNC input⁽¹⁾	SYNC to falling edge of BIT_CLK	10	3.8		ns
T_SHOLD	Hold Time for codec SYNC input⁽¹⁾	Hold time of SYNC from falling edge of BIT_CLK	10			ns
T_CO	Output Valid Delay	Output Delay of SDATA_IN from rising edge of BIT_CLK		5.2	15	ns
T_RISE	Rise Time⁽¹⁾	BIT_CLK, SYNC, SDATA_IN or SDATA_OUT			6	ns
T_FALL	Fall Time⁽¹⁾	BIT_CLK, SYNC, SDATA_IN or SDATA_OUT			6	ns
T_{RST_LOW}	RESET# active low pulse width⁽¹⁾	For Cold Reset	1			µs
T_RST2CLK	RESET# inactive to BIT_CLK start up	For Cold Reset	162.8	271		ns
T_SH	SYNC active high pulse width⁽¹⁾	For Warm Reset	1			µs
T_SYNC2CLK	SYNC inactive to BIT_CLK start up	For Warm Reset	162.8			ns
T_{S2_PDOWN}	AC Link Power Down Delay	Delay from end of Slot 2 to BIT_CLK, SDATA_IN low			1	µs
T_SUPPLY2RST	Power-On Reset	Time from minimum valid supply levels to end of Reset	1			µs
T_SU2RST	Setup to trailing edge of RESET#⁽¹⁾	For ATE Test Mode	15			ns
T_RST2HZ	Rising edge of RESET# to Hi-Z⁽¹⁾	For ATE Test Mode			25	ns