8.3.1 ADC inputs and Outputs

All four of the stereo analog inputs and three of the mono analog inputs can be selected for conversion by the 18-bit stereo ADC. Digital output from the left and right channel ADCs is always located in AC Link Input Frame slots 3 and 4 respectively. Input level to either ADC channel can be muted or adjusted from the Record Gain register, 1Ch. Adjustments are in 1.5-dB steps over a gain range of 0 dB to +22.5 dB and both channels mute together (D15). Input selection for the ADC is through the Record Select Mux controlled from the Record Select register, 1Ah, together with microphone selection controlled by the MS bit (D8) in the General Purpose register, 20h. One of the stereo inputs, CD_IN, uses a quasi-differential 3-pin interface where both stereo channel inputs are referenced to the third pin, CD_GND. CD_GND should be AC coupled to the source ground and provides common-mode feedback to cancel ground noise. It is not a DC ground. The other three stereo inputs, LINE_IN, AUX and VIDEO are 2-pin interfaces, single-ended for each stereo channel, with analog ground (AV_SS) as the signal reference. Either of the two mono microphone inputs can be muxed to a programmable boost amplifier before selection for either channel of the ADC. The Microphone Mux is controlled by the Microphone Selection (MS) bit (D8) in the General Purpose register (20h) and the 20 dB programmable boost is enabled by the 20dB bit (D6) in register 0Eh. The mono PHONE input may also be selected for either ADC channel.

8.3.2 Analog Mixing: MIX1

Five analog inputs are available for mixing at the stereo mixer, MIX1 – all four stereo and one mono, namely the microphone input selected by MS (D8, reg 20h). Digital input to the codec can be directed to either MIX1 or to MIX2 after conversion by the 18-bit stereo DAC and level adjustment by the PCM Out Volume control register (18h). Each input to MIX1 may be muted or level adjusted using the appropriate Mixer Input Volume Register: Mic Volume (0Eh), Line_In Volume (10h), CD Volume (12h), Video Volume (14h), Aux Volume (16h) and PCM Out Volume (18h). The mono microphone input is mixed equally into left and right stereo channels but stereo mixing is orthogonal, that is, left channels are only mixed with other left channels and right with right. The left and right amplitudes of any stereo input may be adjusted independently however mute for a stereo input acts on both left and right channels.

8.3.3 DAC Mixing and 3D Processing

Control of routing the DAC output to MIX1 or MIX2 is by the POP bit (D15) in the General Purpose register, 20h. If MIX1 is selected (default, POP = 0) then the DAC output is available for processing by the TI 3D Sound circuitry. If MIX2 is selected, the DAC output will bypass the 3D processing. This allows analog inputs to be enhanced by the analog 3D Sound circuitry before mixing with digital audio. The digital audio may then use alternative digital 3D enhancements. TI 3D Sound circuitry is enabled by the 3D bit (D13) in the General Purpose register, 20h, and is a fixed depth implementation. The 3D Control register, 22h, is therefore not programmable (read-only). The 3D Sound circuitry defaults to disabled after reset.

8.3.4 Analog Mixing: MIX2

MIX2 combines the output of MIX1 (Stereo Mix 3D) with the two mono analog inputs, PHONE and PC_BEEP; each are level-adjusted by the input control registers Phone Volume (0Ch) and PC_Beep Volume (0Ah) respectively. If selected by the POP bit (D15, reg 20h), the DAC output is also summed into MIX2.

8.3.5 Stereo Mix

The output of MIX2 is the signal, Stereo Mix. Stereo Mix is used to drive both the Headphone output (HP_OUT) and the Line output (LINE_OUT) and can also be selected as the input to the ADC at the Record Select Mux. In addition, the two channels of Stereo Mix are summed to form a mono signal (Mono Mix) also selectable at the Record Select Mux as an input to either channel of the ADC.

8.3.6 Stereo Outputs

The output volume from LINE_OUT and HP_OUT can be muted or adjusted by 0 dB to 45 dB in nominal 3-dB steps under the control of the output volume registers Master Volume (02h) and Headphone Volume (04h) respectively. As with the input volume registers, adjustments to the levels of the two stereo channels can be made independently but both left and right channels share a mute bit (D15).

8.3.7 Mono Output

The mono output (MONO_OUT) is driven by one of two signals selected by the MIX bit (D9) in the General Purpose register, 20h. The signal selected by default (MIX = 0) is the mono summation of the two channels of Stereo Mix 3D, the stereo output of the mixer MIX1. Setting the control bit MIX = 1, selects a microphone input, MIC1 or MIC2. The choice of microphone is controlled by the Microphone Select (MS) bit (D8) also in the General Purpose register, 20h.

8.3.8 Analog Loopthrough And Digital Loopback

Analog Loopthrough refers to an all-analog signal path from an analog input through the mixers to an analog output. Digital Loopback refers to a mixed-mode analog and digital signal path from an analog input through the ADC, looped-back (LPBK bit – D7, 20h) through the DAC and mixers to an analog output. This is an 18 bit digital loopback, bypassing the SRC logic, even if a rate other than 48 kHz is selected.

8.3.9 Resets

COLD RESET is performed when RESET# (pin 11) is pulled low for > 1 µs. It is a complete reset. All registers and internal circuits are reset to their default state. It is the only reset which clears the ATE and Vendor Test Modes.

WARM RESET is performed when SYNC (pin 10) is held high for > 1 µs and the codec AC Link digital interface is in power down (PR4 = 1, Power-down Control / Status register, 26h). It is used to clear PR4 and power up the AC Link digital interface but otherwise does not change the contents of any registers nor reset any internal circuitry.

REGISTER RESET is performed when any value is written to the RESET register, 00h. It resets all registers to their default state and will modify circuit configurations accordingly but does not reset any other internal circuits.

8.3.10 Multiple Codecs

Figure 16. Multiple Codecs using Extended AC Link

8.3.10.2.3 CODEC Chaining

Using TI's unique feature for chaining together codecs, a multiple codec system can be built using fewer interface pins. This Chain feature allows two, three or four codecs to share a single signal input pin at the controller. By setting the two LSBs of the Chain-In Control register (74h) to a value other than the Codec Identity, a controller can instruct a codec to disconnect its own SDATA_IN signal and discard its own Input Frame and instead switch the signal connected to the CIN pin through to the SDATA_IN output pin allowing passage of an SDATA_IN signal carrying the Input Frame from a codec further down the chain. The Chain-In Control register (74h) is updated at the rising edge of SYNC therefore an instruction to enable or disable the Chain feature takes effect in the next frame.

When the Chain feature is used the CIN pin should always be driven. Connect CIN to either the SDATA_IN pin from another codec or else ground CIN to prevent the possibility of floating the SDATA_IN signal at the controller.

Figure 17. Multiple Codecs in a Chain

8.4.1 Test Modes

AC '97 Rev 2.1 defines two test modes: ATE test mode and Vendor test mode. Cold Reset is the only way to exit either of them. The ATE test mode is activated if SDATA_OUT is sampled high by the trailing edge (zero-to-one transition) of RESET#. In ATE test mode, the codec AC Link outputs SDATA_IN and BIT_CLK are configured to a high impedance state to allow tester control of the AC Link interface for controller testing. ATE test mode timing parameters are given in the Electrical Characteristics table. The Vendor test mode is entered if SYNC is sampled high by the zero-to-one transition of RESET#. Neither of these entry conditions can occur in normal AC Link operation but care must be taken to avoid mistaken activation of the test modes when using non standard controllers.

8.5.1 AC Link Serial Interface Protocol

Figure 18. AC Link Bidirectional Audio Frame

Figure 19. AC Link Output Frame

8.5.1.1 AC Link Output Frame: SDATA_OUT, Controller Output to LM4550B Input

The AC Link Output Frame carries control and PCM data to the LM4550B control registers and stereo DAC. Output Frames are carried on the SDATA_OUT signal which is an output from the AC '97 Digital Controller and an input to the LM4550B codec. As shown in Figure 18, Output Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. Each Frame consists of 256 bits with each of the twelve Data Slots containing 20 bits. Input and Output Frames are aligned to the same SYNC transition. The LM4550B only accepts data in eight of the twelve Data Slots and, because it is a two channel codec only in 4 simultaneously – 2 for control, one each for PCM data to the left and right channel DACs. Data-Slot to DAC mappings are tied to the codec mode selected by the Identity pins ID1#, ID0# and are given in Table 1.

A new Output Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller on a rising edge of BIT_CLK and, as shown in Figure 19 and Figure 20, the first tag bit in the Frame (“Valid Frame”) should be clocked from the controller by the next rising edge of BIT_CLK and sampled by the LM4550B on the following falling edge. The AC '97 Controller should always clock data to SDATA_OUT on a rising edge of BIT_CLK and the LM4550B always samples SDATA_OUT on the next falling edge. SYNC is sampled with the falling edge of BIT_CLK.

The LM4550B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high transition on SYNC) before 256 bits are received from the old Frame then the new Frame is ignored, that is, the data on SDATA_OUT is discarded until a valid new Frame is detected.

The LM4550B expects to receive data MSB first, in an MSB justified format.

8.5.1.1.1 SDATA_OUT: Slot 0 – Tag Phase

The first bit of Slot 0 is designated the Valid Frame bit. If this bit is 1, it indicates that the current Output Frame contains at least one slot of valid data and the LM4550B will check further tag bits for valid data in the expected Data Slots. With the codec in Primary mode, a controller will indicate valid data in a slot by setting the associated tag bit equal to 1. Because it is a two channel codec the LM4550B can only receive data from four slots in a given frame and so only checks the valid-data bits for 4 slots. In Primary mode these tag bits are for: slot 1 (Command Address), slot 2 (Command Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data for right DAC).

The last two bits in the Tag contain the Codec ID used to select the target codec to receive the frame in multiple codec systems. When the frame is being sent to a codec in one of the Secondary modes the controller does not use bits 14 and 13 to indicate valid Command Address and Data in slots 1 and 2. Instead, this role is performed by the Codec ID bits – operation of the Extended AC Link assumes that the controller would not access a secondary codec unless it was providing valid Command Address and/or Data. When in one of the secondary modes the LM4550B only checks the tag bits for the Codec ID and for valid data in the two audio data slots: slots 3 & 4 for Secondary mode 1, slots 7 & 8 for mode 2 and slots 6 & 9 for mode 3.

When sending an Output Frame to a Secondary mode codec, a controller should set tag bits 14 and 13 to zero.

Figure 20. Start of AC Link Output Frame

Table 2. Slot 0, Output Frame

BIT	DESCRIPTION	COMMENT
15	Valid Frame	1 =	Valid data in at least one slot.
14	Control register address	1 =	Valid Control Address in Slot 1 (Primary codec only)
13	Control register data	1 =	Valid Control Data in Slot 2 (Primary codec only)
12	Left DAC data in Slot 3	1 =	Valid PCM Data in Slot 3 (Primary & Secondary 1 modes; Left Channel audio)
11	Right DAC data in Slot 4	1 =	Valid PCM Data in Slot 4 (Primary & Secondary 1 modes; Right Channel audio)
10	Not Used	Controller should stuff this slot with “0”s
9	Left DAC data in Slot 6	1 =	Valid PCM Data in Slot 6 (Secondary 3 mode; Center Channel audio)
8	Left DAC data in Slot 7	1 =	Valid PCM Data in Slot 7 (Secondary 2 mode; Left Surround Channel audio)
7	Right DAC data in Slot 8	1 =	Valid PCM Data in Slot 8 (Secondary 2 mode; Right Surround Channel audio)
6	Right DAC data in Slot 9	1 =	Valid PCM Data in Slot 9 (Secondary 3 mode; LFE Channel audio)
5:2	Not Used	Controller should stuff these slots with “0”s
1,0	Codec ID (ID1, ID0)	The Codec ID (Table 1) selects the target codec in a multi-codec system to receive the control address and data carried in the Output Frame

8.5.1.1.2 SDATA_OUT: Slot 1 – Read/Write, Control Address

Slot 1 is used by a controller to indicate both the address of a target register in the LM4550B and whether the access operation is a register read or register write. The MSB of slot 1 (bit 19) is set to 1 to indicate that the current access operation is read. Bits 18 through 12 are used to specify the 7-bit register address of the read or write operation. The least significant twelve bits are reserved and should be stuffed with zeros by the AC '97 controller.

Table 3. Slot 1, Output Frame

BIT	DESCRIPTION	COMMENT
19	Read/Write	1 = Read 0 = Write
18:12	Register Address	Identifies the Status/Command register for read/write
11:0	Reserved	Controller should set to 0

8.5.1.1.3 SDATA_OUT: Slot 2 – Control Data

Slot 2 is used to transmit 16-bit control data to the LM4550B when the access operation is write. The least significant four bits should be stuffed with zeros by the AC '97 controller. If the access operation is a register read, the entire slot, bits 19 through 0 should be stuffed with zeros.

Table 4. Slot 2, Output Frame

BIT	DESCRIPTION	COMMENT
19:4	Control Register Write Data	Controller should stuff with zeros if operation is read
3:0	Reserved	Set to 0

8.5.1.1.4 SDATA_OUT: Slots 3 & 4 – PCM Playback Left/Right Channels

Slots 3 and 4 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when the codec is in Primary mode or Secondary mode 1. Any unused bits should be stuffed with zeros. The LM4550B DACs have 18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). The AC '97 Rev 2.1 specification allocates the Left channel of 5.1 Audio to slot 3 and the Right channel to slot 4.

Table 5. SLOTS 3 & 4, OUTPUT FRAME

BIT	DESCRIPTION	COMMENT
19:0	PCM Audio Data (Left /Right Channels)	Slots used to stream data to DAC when codec is in Primary or Secondary 1 modes. Set unused bits to 0

8.5.1.1.5 SDATA_OUT: Slots 7 & 8 – PCM Playback Left/Right Surround

Slots 7 and 8 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when the codec is in Secondary mode 2. Any unused bits should be stuffed with zeros. The LM4550B DACs have 18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). The AC '97 Rev 2.1 specification allocates the Left Surround channel of 5.1 Audio to slot 7 and the Right Surround channel to slot 8.

Table 6. Slots 7 and 8, Output Frame

BIT	DESCRIPTION	COMMENT
19:0	PCM Audio Data (Left/Right Surround)	Slots used to stream data to DAC when codec is in Secondary 2 mode. Set unused bits to 0

8.5.1.1.6 SDATA_OUT: Slots 6 & 9 – PCM Playback (Center/LFE)

Slots 6 and 9 are 20-bit fields used to transmit PCM data to the left and right channels of the stereo DAC when the codec is in Secondary mode 3. Any unused bits should be stuffed with zeros. The LM4550B DACs have 18-bit resolution and will therefore use the 18 MSBs of the 20-bit PCM data (MSB justified). The AC '97 Rev 2.1 specification allocates the Center channel of 5.1 Audio to slot 6 and the LFE (Low Frequency Enhancement) channel to slot 9.

Table 7. Slots 6 and 9, Output Frame

BIT	DESCRIPTION	COMMENT
19:0	PCM Audio Data (Center/ LFE Surround)	Slots used to stream data to DAC when codec is in Secondary 3 mode. Set unused bits to 0

8.5.1.1.7 SDATA_OUT: Slots 5, 10, 11, 12 – Reserved

These slots are unused by the LM4550B and should all be stuffed with zeros by the AC '97 Controller.

Figure 21. AC Link Input Frame

8.5.1.2 AC Link Input Frame: SDATA_IN, Controller Input from LM4550B Output

The AC Link Input Frame contains status and PCM data from the LM4550B control registers and stereo ADC. Input Frames are carried on the SDATA_IN signal which is an input to the AC '97 Digital Audio Controller and an output from the LM4550B codec. As shown in Figure 18, Input Frames are constructed from thirteen time slots: one Tag Slot followed by twelve Data Slots. The Tag Slot, Slot 0, contains 16 bits of which 5 are used by the LM4550B. One is used to indicate that the AC Link interface is fully operational and the other 4 to indicate the validity of the data in the four of the twelve following Data Slots that are used by the LM4550B. Each Frame consists of 256 bits with each of the twelve data slots containing 20 bits.

A new Input Frame is signaled with a low-to-high transition of SYNC. SYNC should be clocked from the controller on a rising edge of BIT_CLK and, as shown in Figure 21 and Figure 22, the first tag bit in the Frame (Codec Ready) is clocked from the LM4550B by the next rising edge of BIT_CLK. The LM4550B always clocks data to SDATA_IN on a rising edge of BIT_CLK and the controller is expected to sample SDATA_IN on the next falling edge. The LM4550B samples SYNC on the falling edge of BIT_CLK.

Input and Output Frames are aligned to the same SYNC transition.

The LM4550B checks each Frame to ensure 256 bits are received. If a new Frame is detected (a low-to-high transition on SYNC) before 256 bits are received from an old Frame then the new Frame is ignored, that is, no valid data is sent on SDATA_IN until a valid new Frame is detected.

The LM4550B transmits data MSB first, in an MSB justified format. All reserved bits and slots are stuffed with 0s by the LM4550B.

Figure 22. Start of AC Link Input Frame

8.5.1.2.1 SDATA_IN: Slot 0 – Codec/Slot Status Bits

The first bit (bit 15, Codec Ready) of slot 0 in the AC Link Input Frame indicates when the codec's AC Link digital interface and its status/control registers are fully operational. The digital controller is then able to read the LSBs from the Power-down Control/Stat register (26h) to determine the status of the four main analog subsections. It is important to check the status of these subsections after Initialization, Cold Reset or the use of the power-down modes to minimize the risk of distorting analog signals passed before the subsections are ready.

The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1, 2, 3 and 4, respectively, are valid.

Table 8. Slot 0, Input Frame

BIT	DESCRIPTION	COMMENT
15	Codec Ready Bit	1 =	AC Link Interface Ready
14	Slot 1 data valid	1 =	Valid Status Address or Slot Request
13	Slot 2 data valid	1 =	Valid Status Data
12	Slot 3 data valid	1 =	Valid PCM Data (Left ADC)
11	Slot 4 data valid	1 =	Valid PCM Data (Right ADC)

8.5.1.2.2 SDATA_IN: Slot 1 – Status Address / Slot Request Bits

This slot echoes (in bits 18 – 12) the 7-bit address of the codec control/status register received from the controller as part of a read-request in the previous frame. If no read-request was received, the codec stuffs these bits with zeros.

The 6 bits 11, 10, 8 – 5 are Slot Request bits that support the Variable Rate Audio (VRA) capabilities of the LM4550B. Only two are used simultaneously. If the codec is in Primary mode or Secondary mode 1, then the left and right channels of the DAC take PCM data from slots 3 and 4 in the Output Frame respectively (see Table 1). The codec uses bits 11 and 10 to request DAC data from these two slots. If bits 11 and 10 are set to 0, the controller should respond with valid PCM data in slots 3 and 4 of the next Output Frame. If bits 11 and 10 are set to 1, the controller should not send data. Similarly, if the codec is in Secondary mode 2, bits 7 and 6 are used to request data from slots 7 and 8 in the Output Frame. If in Secondary mode 3, bits 8 and 5 request data from slots 6 and 9.

The codec has full control of the slot request bits. By default, data is requested in every frame, corresponding to a sample rate equal to the frame rate (SYNC frequency) – 48 kHz when XTAL_IN = 24.576 MHz. To send samples at a rate below the frame rate, a controller should set VRA = 1 (bit 0 in the Extended Audio Control/Status register, 2Ah) and program the desired rate into the PCM DAC Rate register, 2Ch. Both DAC channels operate at the same sample rate. Values for common sample rates are given in the Register Descriptions section (Sample Rate Control Registers, 2Ch, 32h) but any rate between 4 kHz and 48 kHz (to a resolution of 1 Hz) is supported. Slot Requests from the LM4550B are issued completely deterministically. For example if a sample rate of 8000 Hz is programmed into 2Ch then the LM4550B will always issue a slot request in every sixth frame. A frequency of 9600 Hz will result in a request every fifth frame while a frequency of 8800 Hz will cause slot requests to be spaced alternately five and six frames apart. This determinism makes it easy to plan task scheduling on a system controller and simplifies application software development.

The LM4550B will ignore data in Output Frame slots that do not follow an Input Frame with a Slot Request. For example, if the LM4550B is expecting data at a 8000 Hz rate yet the AC '97 Digital Audio Controller continues to send data at 48000 Hz, then only those one-in-six audio samples that follow a Slot Request will be used by the DAC. The rest will be discarded.

Bits 9, 4, 3, and 2 are request bits for slots not used by the LM4550B and are stuffed with zeros. Bits 1 and 0 are reserved and are also stuffed with zeros.

Table 9. SLOT 1, INPUT FRAME

BITS	DESCRIPTION	COMMENT
19	Reserved	Stuffed with 0 by LM4550B
18:12	Status Register Index	Echo of the requested Status Register address.
11	Slot 3 Request bit (PCM Left Audio)	0 =	Controller should send valid data in Slot 3 of the next Output Frame.
		1 =	Controller should not send Slot 3 data.
10	Slot 4 Request bit (PCM Right Audio)	0 =	Controller should send valid data in Slot 4 of the next Output Frame.
		1 =	Controller should not send Slot 4 data.
9	Slot 5 Request bit	Unused - set to 0 by LM4550B
8	Slot 6 Request bit (PCM Center)	0 =	Controller should send valid data in Slot 6 of the next Output Frame.
		1 =	Controller should not send Slot 6 data.
7	Slot 7 Request bit (PCM Left Surround)	0 =	Controller should send valid Slot 7 data in the next Output Frame.
		1 =	Controller should not send Slot 7 data.
6	Slot 8 Request bit (PCM Right Surround)	0 =	Controller should send valid data in Slot 8 of next Output Frame.
		1 =	Controller should not send Slot 8 data.
5	Slot 9 Request bit (PCM LFE)	0 =	Controller should send valid data in Slot 9 of next Output Frame.
		1 =	Controller should not send Slot 9 data.
4:2	Unused Slot Request bits	Stuffed with 0s by LM4550B
1,0	Reserved	Stuffed with 0s by LM4550B

8.5.1.2.3 SDATA_IN: Slot 2 – Status Data

This slot returns 16-bit status data read from a codec control/status register. The codec sends the data in the frame following a read-request by the controller (bit 15, slot 1 of the Output Frame). If no read-request was made in the previous frame the codec will stuff this slot with zeros.

Table 10. SLOT 2, INPUT FRAME

BITS	DESCRIPTION	COMMENT
19:4	Status Data	Data read from a codec control/status register. Stuffed with 0s if no read-request in previous frame.
3:0	Reserved	Stuffed with 0s by LM4550B

8.5.1.2.4 SDATA_IN: Slot 3 – PCM Record Left Channel

This slot contains sampled data from the left channel of the stereo ADC. The signal to be digitized is selected using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record Gain amplifier to the ADC.

This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2 LSBs are stuffed with zeros.

Table 11. SLOT 3, INPUT FRAME

BITS	DESCRIPTION	COMMENT
19:2	PCM Record Left Channel data	18-bit PCM audio sample from left ADC
1:0	Reserved	Stuffed with 0s by LM4550B

8.5.1.2.5 SDATA_IN: Slot 4 – PCM Record Right Channel

This slot contains sampled data from the right channel of the stereo ADC. The signal to be digitized is selected using the Record Select register (1Ah) and subsequently routed through the Record Select Mux and the Record Gain amplifier to the ADC.

This is a 20-bit slot and the digitized 18-bit PCM data is transmitted in an MSB justified format. The remaining 2 LSBs are stuffed with zeros.

Table 12. SLOT 4, INPUT FRAME

BITS	DESCRIPTION	COMMENT
19:2	PCM Record Right Channel data	18-bit PCM audio sample from right ADC
1:0	Reserved	Stuffed with 0s by LM4550B

8.5.1.2.6 SDATA_IN: Slots 5 to 12 – Reserved

Slots 5 to 12 of the AC Link Input Frame are unused for data by the LM4550B and are always stuffed with zeros.

8.6.1 LM4550B Register Map

8.6.2 Register Descriptions

Default settings are indicated by *.

8.6.3 Reset Register (00h)

Writing any value to this register causes a Register Reset which changes all registers back to their default values. If a read is performed on this register, the LM4550B will return a value of 0D50h. This value can be interpreted in accordance with the AC '97 specification to indicate that TI 3D Sound is implemented, 18-bit data is supported for both the ADCs and DACs, and that headphone output is supported.

8.6.4 Master Volume Register (02h)

This output register allows the output level from either channel of the stereo LINE_OUT to be muted or attenuated from 0 dB to 46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control for each channel and both stereo channels can be individually attenuated. The mute bit (D15) acts simultaneously on both stereo channels of LINE_OUT. The AC'97 specification states that “support for the MSB of the level is optional.” All six bits may be written to the register, but if the MSB is a 1, the MSB is ignored and the register will be set to 0 11111. This will be the value when the register is read, allowing the software driver to detect whether the MSB is supported or not.

8.6.5 Headphone Volume Register (04h)

This output register allows the level from both channels of HP_OUT to be muted or individually attenuated from 0 dB to 46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control for each channel plus one mute bit. The mute bit (D15) acts on both channels. Operation of this register and HP_OUT matches that of the Master Volume register and the LINE_OUT output. All six bits may be written to the register, but if the MSB is a 1, the MSB is ignored and the register will be set to 0 11111. This will be the value when the register is read, allowing the software driver to detect whether the MSB is supported or not

8.6.6 Mono Volume Register (06h)

This output register allows the level from MONO_OUT to be muted or attenuated from 0 dB to 46.5 dB in nominal 1.5-dB steps. There are 6 bits of volume control and one mute bit (D15). All six bits may be written to the register, but if the MSB is a 1, the MSB is ignored and the register will be set to 0 11111. This will be the value when the register is read, allowing the software driver to detect whether the MSB is supported or not.

8.6.7 PC Beep Volume Register (0Ah)

This input register adjusts the level of the mono PC_BEEP input to the stereo mixer MIX2, where it is summed equally into both channels of the Stereo Mix signal. PC_BEEP can be both muted and attenuated from 0 dB to 45 dB in nominal 3-dB steps.

8.6.8 Mixer Input Volume Registers (Index 0Ch – 18h)

These input registers adjust the volume levels into the stereo mixers MIX1 and MIX2. Each channel may be adjusted from 12-dB gain to 34.5-dB attenuation in 1.5-dB steps. For stereo ports, volumes of the left and right channels can be independently adjusted. Muting a given port is accomplished by setting the MSB to 1. Setting the MSB to 1 for stereo ports mutes both the left and right channels. The Mic Volume register (0Eh) controls an additional 20 dB boost for the selected microphone input by setting the 20 dB bit (bit D6).

8.6.9 Record Select Register (1Ah)

This register independently controls the sources for the right and left channels of the stereo ADC. The default value of 0000h corresponds to selecting the (mono) Mic input for both channels.

8.6.10 Record Gain Register (1Ch)

This register controls the input levels for both channels of the stereo ADC. The inputs come from the Record Select Mux and are selected through the Record Select Control register, 1Ah. The gain of each channel can be individually programmed from 0dB to 22.5dB in 1.5-dB steps. Both channels can also be muted by setting the MSB to 1.

8.6.11 General Purpose Register (20h)

This register controls many miscellaneous functions implemented on the LM4550B. The miscellaneous control bits include POP which allows the DAC output to bypass the TI 3D Sound circuitry, 3D which enables or disables the TI 3D Sound circuitry, MIX which selects the MONO_OUT source, MS which controls the Microphone Selection mux and LPBK which connects the output of the stereo ADC to the input of the stereo DAC. LPBK provides a mixed-mode analog-digital-analog loopback path between analog inputs and analog outputs. This is an 18 bit digital loopback.

8.6.12 3D Control Register (22h)

This read-only (0101h) register indicates, in accordance with the AC '97 Rev 2.1 Specification, the fixed depth and center characteristics of the TI 3D Sound stereo enhancement.

8.6.13 Power-Down Control / Status Register (26h)

This read/write register is used both to monitor subsystem readiness and also to program the LM4550B power-down states. The 4 LSBs indicate status and the 8 MSBs control power down.

The 4 LSBs of this register indicate the status of the 4 audio subsections of the codec: Reference voltage, Analog mixers and amplifiers, DAC section, ADC section. When the Codec Ready indicator bit in the AC Link Input Frame (SDATA_IN: slot 0, bit 15) is a 1, it indicates that the AC Link and AC '97 registers are in a fully operational state and that control and status information can be transferred. It does not indicate that the codec is ready to send or receive audio PCM data or to pass signals through the analog I/O and mixers. To determine that readiness, the Controller must check that the 4 LSBs of this register are set to “1” indicating that the appropriate audio subsections are ready.

The power-down bits PR0 – PR6 control internal subsections of the codec. They are implemented in compliance with AC '97 Rev 2.1 to support the standard device power management states D0 – D3 as defined in the ACPI and PCI Bus Power Management specification.

PR0 controls the power-down state of the ADC and associated sampling rate conversion circuitry. PR1 controls power down for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits (MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down V_REF in addition to all the same mixer circuits as PR2. PR4 powers down the AC Link digital interface – see Figure 23 for signal power-down timing. PR5 disables internal clocks. PR6 powers down the Headphone amplifier. EAPD controls the External Amplifier Power-Down bit.

8.6.14 Extended Audio Id Register (28h)

This read-only (X201h) register identifies which AC '97 Extended Audio features are supported. The LM4550B features AMAP (Slot/DAC mappings based on Codec Identity), VRA (Variable Rate Audio) and ID1, ID0, the Codec Identity bits used to support multi-codec systems. AMAP is indicated by a 1 in bit 9, VRA is indicated by a 1 in bit 0. The two MSBs, ID1 and ID0, show the current Codec Identity as defined by the Identity pins ID1#, ID0#. The external logic connections to ID1#, ID0# (pins 46 and 45) are inverse in polarity to the value of the Codec Identity (ID1, ID0) held in bits D15, D14. The AMAP Slot/DAC mappings are given in Table 1 in the Multiple Codec section. Codec mode selections are shown in the table below.

8.6.15 Extended Audio Status/control Register (2Ah)

This read/write register provides status and control of the variable sample rate capabilities in the LM4550B. Setting the LSB of this register to 1 enables Variable Rate Audio (VRA) mode and allows DAC and ADC sample rates to be programmed through registers 2Ch and 32h respectively.

8.6.16 Sample Rate Control Registers (2Ch, 32h)

These read/write registers are used to set the sample rate for the left and right channels of the DAC (PCM DAC Rate, 2Ch) and the ADC (PCM ADC Rate, 32h). When Variable Rate Audio is enabled through bit 0 of the Extended Audio Control/Status register (2Ah), the sample rates can be programmed, in 1 Hz increments, to be any value from 4 kHz to 48 kHz. The value required is the hexadecimal representation of the desired sample rate, that is, 8000₁₀ = 1F40h. Below is a list of the most common sample rates and the corresponding register (hex) values.

8.6.17 Chain-in Control Register (74h)

This read/write register is only needed when using the Chain In feature. This feature goes beyond the AC '97 specification and is not required for standard AC Link operation. The two LSBs of this register default to the Codec Identity (ID1, ID0) after reset. This default state corresponds to standard AC Link operation where the output of codec pin 8 (SDATA_IN) carries the AC Link Input Frames back to the controller from the codec.

If the two LSBs differ from the Codec Identity (register 28h describes the Codec Identity), then the signal present at CIN (pin 48) is switched through to the SDATA_IN (pin 8) output. In this fashion, Secondary codecs can be chained together by connecting one codec's SDATA_IN pin to the next codec's CIN pin. This has the end result of only requiring a single SDATA_IN pin at the controller rather than the standard one SDATA_IN pin per codec. Note, however, that the chained codecs time-share the bandwidth of the SDATA_IN signal under allocation from the controller.

The first codec in the chain (nearest the controller) will have access to the full bandwidth of SDATA_IN following a system reset (Cold Reset for each codec). To access any other codec in the chain, the controller must write a suitable value (that is, the Identity of the target codec) to the Chain-In Control register (74h) of each intervening codec in the chain.

The last codec in the serial chain (furthest from the controller) should have its CIN pin connected to digital ground. When writing software drivers, take care to avoid any problems that could occur when this last codec in the chain is set to pass a CIN signal when there is none to pass. Different controllers may handle an input of all 0s differently and leaving the CIN pin floating should definitely be avoided.

8.6.18 Vendor ID Registers (7Ch, 7Eh)

These two read-only (4E53h, 4350h) registers contain TI's Vendor ID and TI's LM45xx codec version designation. The first 24 bits (4Eh, 53h, 43h) represent the three ASCII characters that are the TI Vendor ID for Microsoft's Plug and Play. The last 8 bits are the two binary coded decimal characters, 5, 0 and identify the codec to be an LM4550 family part.

8.6.19 Reserved Registers

Do not write to reserved registers. In particular, do not write to registers 24h, 5Ah and 7Ah. All registers not listed in the LM4550B Register Map are reserved. Reserved registers will return 0000h if read.

8.6.20 Low Power Modes

The LM4550B provides 7 bits to control the power-down state of internal analog and digital subsections and clocks. It also provides one bit intended to control an external analog power amplifier. These 8 bits (PR0 – PR6, EAPD) are the 8 MSBs of the Power-Down Control/Status register, 26h. The status of the four main analog subsections is given by the 4 LSBs in the same register, 26h.

The power-down bits are implemented in compliance with AC '97 Rev 2.1 to support the standard device power management states D0 – D3 as defined in the ACPI and PCI Bus Power Management specification.

PR0 controls the power-down state of the ADC and associated sampling rate conversion circuitry. PR1 controls power down for the DAC and the DAC sampling rate conversion circuitry. PR2 powers down the mixer circuits (MIX1, MIX2, TI 3D Sound, Mono Out, Line Out). PR3 powers down V_REF in addition to all the same mixer circuits as PR2. PR4 powers down the AC Link Digital Interface – see Figure 23 for signal power-down timing. PR5 disables internal clocks but leaves the crystal oscillator and BIT_CLK running (needed for minimum Primary mode power-down dissipation in multi-codec systems). PR6 powers down the Headphone amplifier. EAPD controls the External Amplifier Power-Down pin (pin 47).

After a subsection has undergone a power-down cycle, the appropriate status bit(s) in the Power-down Control/Status register (26h) must be polled to confirm readiness. In particular the startup time of the V_REF circuitry depends on the value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in parallel is recommended).

When the AC Link Digital Interface is powered down the codec output signals SDATA_IN and BIT_CLK (Primary mode) are cleared to zero and no control data can be passed between controller and codec(s). This power-down state can be cleared in two ways: Cold Reset (RESET# = 0) or Warm Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all registers back to their default values (including clearing PR4) whereas Warm Reset only clears the PR4 bit and restarts the AC Link Digital Interface leaving all register contents otherwise unaffected. For Warm Reset (see Timing Diagrams), the SYNC input is used asynchronously. The LM4550B codec allows the AC Link digital interface power-down state to be cleared immediately so that its duration can essentially be as short as T_SH, the Warm Reset pulse width. However for conformance with AC '97 Rev 2.1, Warm Reset should not be applied within 4 frame times of power down, that is, the AC Link power-down state should be allowed to last at least 82.8 µs.