SNVSAA2B July   2015  – July 2017 LM46002-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency Peak Current Mode Controlled Step-Down Regulator
      2. 7.3.2  Light Load Operation
      3. 7.3.3  Adjustable Output Voltage
      4. 7.3.4  Enable (ENABLE)
      5. 7.3.5  VCC, UVLO and BIAS
      6. 7.3.6  Soft-Start and Voltage Tracking (SS/TRK)
      7. 7.3.7  Switching Frequency (RT) and Synchronization (SYNC)
      8. 7.3.8  Minimum ON-Time, Minimum OFF-Time and Frequency Foldback at Dropout Conditions
      9. 7.3.9  Internal Compensation and CFF
      10. 7.3.10 Bootstrap Voltage (BOOT)
      11. 7.3.11 Power Good (PGOOD)
      12. 7.3.12 Overcurrent and Short-Circuit Protection
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Stand-by Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 CCM Mode
      5. 7.4.5 Light Load Operation
      6. 7.4.6 Self-Bias Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feed-Forward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitor
        10. 8.2.2.10 BIAS Capacitors
        11. 8.2.2.11 Soft-Start Capacitors
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
      3. 8.2.3 Application Performance Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact Layout for EMI Reduction
      2. 10.1.2 Ground Plane and Thermal Considerations
      3. 10.1.3 Feedback Resistors
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
Input voltages VIN to PGND –0.3 65 V
EN to PGND –0.3 VIN + 0.3
FB, RT, SS/TRK to AGND –0.3 3.6
PGOOD to AGND –0.3 15
SYNC to AGND –0.3 5.5
BIAS to AGND –0.3 30
AGND to PGND –0.3 0.3
Output voltages SW to PGND –0.3 VIN + 0.3 V
SW to PGND less than 10ns Transients –3.5 65
CBOOT to SW –0.3 5.5
VCC to AGND –0.3 3.6
Storage temperature range, Tstg –65 150 °C
Operating junction temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
Input voltages VIN to PGND 3.5 60 V
EN –0.3 VIN
FB –0.3 1.1
PGOOD –0.3 12
BIAS input not used –0.3 0.3
BIAS input used 3.3 28
AGND to PGND –0.1 0.1
Output voltage VOUT 1 28 V
Output current IOUT 0 2 A
Temperature Operating junction temperature range, TJ –40 125 °C
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For verified specifications, see Electrical Characteristics.

6.4 Thermal Information

THERMAL METRIC (1)(2) LM46002-Q1 UNIT
PWP (HTSSOP)
(16 PINS)
RθJA Junction-to-ambient thermal resistance 38.9(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.3 °C/W
RθJB Junction-to-board thermal resistance 19.9 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 19.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7 standard with a 4-layer board and 2-W power dissipation.
(3) RθJA is highly related to PCB layout and heat sinking. Please refer to Figure 101 for measured RθJA vs PCB area from a 2-layer board and a 4-layer board.

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PINS)
VIN-MIN-ST Minimum input voltage for start-up 3.8 V
ISHDN Shutdown quiescent current VEN = 0 V 2.3 5 µA
IQ-NONSW Operating quiescent current (non-switching) from VIN VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external		 7 12 µA
IBIAS-NONSW Operating quiescent current (non-switching) from external VBIAS VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external		 87 135 µA
IQ-SW Operating quiescent current (switching) VEN = VIN
IOUT = 0 A
RT = open
VBIAS = VOUT = 3.3 V
RFBT = 1 Meg		 27 µA
ENABLE (EN PIN)
VEN-VCC-H Voltage level to enable the internal LDO output VCC VENABLE high level 1.2 V
VEN-VCC-L Voltage level to disable the internal LDO output VCC VENABLE low level 0.4 V
VEN-VOUT-H Precision enable level for switching and regulator output: VOUT VENABLE high level 2 2.1 2.42 V
VEN-VOUT-HYS Hysteresis voltage between VOUT precision enable and disable thresholds VENABLE hysteresis –294 mV
ILKG-EN Enable input leakage current VEN = 3.3 V 0.8 1.7 µA
INTERNAL LDO (VCC PIN AND BIAS PIN)
VCC Internal LDO output voltage VCC VIN ≥ 3.8 V 3.2 V
VCC-UVLO Undervoltage lock out (UVLO) thresholds for VCC VCC rising threshold 3.15 V
Hysteresis voltage between rising and falling thresholds –575 mV
VBIAS-ON Internal LDO input change over threshold to BIAS VBIAS rising threshold 2.94 3.15 V
Hysteresis voltage between rising and falling thresholds –67 mV
VOLTAGE REFERENCE (FB PIN)
VFB Feedback voltage TJ = 25°C 1.004 1.011 1.018 V
TJ = –40°C to 125°C 0.994 1.011 1.030
ILKG-FB Input leakage current at FB pin FB = 1.011 V 0.2 65 nA
THERMAL SHUTDOWN
TSD (1) Thermal shutdown Shutdown threshold 160 °C
Recovery threshold 150 °C
CURRENT LIMIT AND HICCUP
IHS-LIMIT Peak inductor current limit 3.6 4.5 5 A
ILS-LIMIT Valley inductor current limit 1.8 2.05 2.3 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.17 2 2.75 µA
RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = 0 V 16 kΩ
POWER GOOD (PGOOD PIN)
VPGOOD-HIGH Power-good flag overvoltage tripping threshold % of FB voltage 110% 113%
VPGOOD-LOW Power-good flag undervoltage tripping threshold % of FB voltage 80% 88%
VPGOOD-HYS Power-good flag recovery hysteresis % of FB voltage 6%
RPGOOD PGOOD pin pull down resistance when power bad VEN = 3.3 V 69 150 Ω
VEN = 0 V 150 350
MOSFETS(2)
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V		 210 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V		 110 mΩ
(1) Ensured by design. Not production tested.
(2) Measured at package pins

6.6 Timing Requirements

PARAMETER MIN NOM MAX UNIT
CURRENT LIMIT AND HICCUP
NOC Hiccup wait cycles when LS current limit tripped 32 Cycles
TOC Hiccup retry delay time 5.5 ms
SOFT START (SS/TRK PIN)
TSS Internal soft-start time when SS pin open circuit 4.1 ms
POWER GOOD (PGOOD PIN)
TPGOOD-RISE Power-good flag rising transition deglitch delay 220 µs
TPGOOD-FALL Power-good flag falling transition deglitch delay 220 µs

6.7 Switching Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SW (SW PIN)
tON-MIN(1) Minimum high side MOSFET ON-time 125 165 ns
tOFF-MIN(1) Minimum high side MOSFET OFF-time 200 250 ns
OSCILLATOR (SW PINS AND SYNC PIN)
FOSC-DEFAULT Oscillator default frequency RT pin open circuit 410 500 590 kHz
FADJ Minimum adjustable frequency With 1% resistors at RT pin 200 kHz
Maximum adjustable frequency 2200 kHz
Frequency adjust accuracy 10%
VSYNC-HIGH Sync clock high level threshold 2 V
VSYNC-LOW Sync clock low level threshold 0.4 V
DSYNC-MAX Sync clock maximum duty cycle 90%
DSYNC-MIN Sync clock minimum duty cycle 10%
TSYNC-MIN Minimum sync clock ON-time and OFF time 80 ns
(1) Ensured by design. Not production tested.

6.8 Typical Characteristics

Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, FS = 500 kHz, L = 10 µH, COUT = 150 µF, CFF = 47 pF. See Application Performance Curves for Bill of Materials (BOM) for other VOUT and FS combinations.
LM46002-Q1 LM46002A-Q1 C001_eff_3p3V_500kHz_snvsa13.png
VOUT = 3.3 V FS = 500 kHz
Figure 1. Efficiency
LM46002-Q1 LM46002A-Q1 C003_eff_5V_500kHz_snvsa13.png
VOUT = 5 V FS = 500 kHz
Figure 3. Efficiency
LM46002-Q1 LM46002A-Q1 C005_eff_12V_500kHz_snvsa13.png
VOUT = 12 V FS = 500 kHz
Figure 5. Efficiency
LM46002-Q1 LM46002A-Q1 C007_voutr_3p3V_500kHz_snvsa13.png
VOUT = 3.3 V FS = 500 kHz
Figure 7. VOUT Regulation
LM46002-Q1 LM46002A-Q1 C009_voutr_5V_500kHz_snvsa13.png
VOUT = 5 V FS = 500 kHz
Figure 9. VOUT Regulation
LM46002-Q1 LM46002A-Q1 C011_voutr_12V_500kHz_snvsa13.png
VOUT = 12 V FS = 500 kHz
Figure 11. VOUT Regulation
LM46002-Q1 LM46002A-Q1 C013_dropo_3p3V_500kHz_snvsa13.png
VOUT = 3.3 V FS = 500 kHz
Figure 13. Dropout Curve
LM46002-Q1 LM46002A-Q1 C015_dropo_5V_500kHz_snvsa13.png
VOUT = 5 V FS = 500 kHz
Figure 15. Dropout Curve
LM46002-Q1 LM46002A-Q1 C017_dropo_12V_500kHz_snvsa13.png
VOUT = 12 V FS = 500 kHz
Figure 17. Dropout Curve
LM46002-Q1 LM46002A-Q1 3p3V_500k_Fsw_Dropout.png
VOUT = 3.3 V FS = 500 kHz
Figure 19. Switching Frequency vs VIN in Dropout Operation
LM46002-Q1 LM46002A-Q1 EMI_Radiated_24V_5V_0p5MHz.png
VOUT = 3.3 V FS = 500 kHz IOUT = 2 A
Measured on the LM46002QPWPEVM with default BOM. No input filter used.
Figure 21. Radiated EMI Curve
LM46002-Q1 LM46002A-Q1 EMI_Conducted_24V_3p3V_2A0p5MHz.png
VOUT = 3.3 V FS = 500 kHz IOUT = 2 A
Measured on the LM46002QPWPEVM with default BOM. Input filter: Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Figure 23. Conducted EMI Curve
LM46002-Q1 LM46002A-Q1 RDSON_OverTemp.png
Figure 25. High-Side and Low-side On-Resistance vs Junction Temperature
LM46002-Q1 LM46002A-Q1 EN_Threshold_OverTemp.png
Figure 27. Enable Threshold vs Junction Temperature
LM46002-Q1 LM46002A-Q1 PGOOD_Limits_OverTemp.png
Figure 29. PGOOD Threshold vs Junction Temperature
LM46002-Q1 LM46002A-Q1 3p3V_500k_PkValleyInductorCurr.png
VOUT = 3.3 V FS = 500 kHz
Figure 31. Peak and Valley Current Limits vs VIN
LM46002-Q1 LM46002A-Q1 C002_eff_5V_200kHz_snvsa13.png
VOUT = 5 V FS = 200 kHz
Figure 2. Efficiency
LM46002-Q1 LM46002A-Q1 C004_eff_5V_1MHz_snvsa13.png
VOUT = 5 V FS = 1 MHz
Figure 4. Efficiency
LM46002-Q1 LM46002A-Q1 C006_eff_24V_500kHz_snvsa13.png
VOUT = 24 V FS = 500 kHz
Figure 6. Efficiency
LM46002-Q1 LM46002A-Q1 C008_voutr_5V_200kHz_snvsa13.png
VOUT = 5 V FS = 200 kHz
Figure 8. VOUT Regulation
LM46002-Q1 LM46002A-Q1 C010_voutr_5V_1MHz_snvsa13.png
VOUT = 5 V FS = 1 MHz
Figure 10. VOUT Regulation
LM46002-Q1 LM46002A-Q1 C012_voutr_24V_500kHz_snvsa13.png
VOUT = 24 V FS = 500 kHz
Figure 12. VOUT Regulation
LM46002-Q1 LM46002A-Q1 C014_dropo_5V_200kHz_snvsa13.png
VOUT = 5 V FS = 200 kHz
Figure 14. Dropout Curve
LM46002-Q1 LM46002A-Q1 C016_dropo_5V_1MHz_snvsa13.png
VOUT = 5 V FS = 1 MHz
Figure 16. Dropout Curve
LM46002-Q1 LM46002A-Q1 C018_dropo_24V_500kHz_snvsa13.png
VOUT = 24 V FS = 500 kHz
Figure 18. Dropout Curve
LM46002-Q1 LM46002A-Q1 5V_1M_Fsw_Dropout.png
VOUT = 5 V FS = 1 MHz
Figure 20. Switching Frequency vs VIN in Dropout Operation
LM46002-Q1 LM46002A-Q1 EMI_Radiated_12V_3p3V_2A_1MHz.png
VOUT = 5 V FS = 1 MHz IOUT = 2 A
Measured on the LM46002QPWPEVM with L = 6.8 µH, COUT = 47 µF, CFF = 47 pF. No input filter used.
Figure 22. Radiated EMI Curve
LM46002-Q1 LM46002A-Q1 EMI_Conducted_24V_V_2A_1MHz.png
VOUT = 5 V FS = 1 MHz IOUT = 2 A
Measured on the LM46002QPWPEVM with L = 6.8 µH, COUT = 47 µF, CFF = 47 pF. Input filter Lin = 1 µH Cd = 47 µF CIN4 = 68 µF
Figure 24. Conducted EMI Curve
LM46002-Q1 LM46002A-Q1 Shutdown_Current_OverTemp.png
Figure 26. Shutdown Current vs Junction Temperature
LM46002-Q1 LM46002A-Q1 EN_Leakage_Current_OverTemp.png
Figure 28. Enable Leakage Current vs
Junction Temperature
LM46002-Q1 LM46002A-Q1 1V_200k_VFB_Temperature.png
Figure 30. Feedback Voltage vs Junction Temperature
LM46002-Q1 LM46002A-Q1 3p3V_500k_Iq.png
i.
VOUT = 3.3 V FS = 500 kHz IOUT = 0 A
EN pin is connected to external 5 V rail
Figure 32. Operation IQ vs VIN with BIAS Connected to VOUT