JAJSAQ4F January 2007 – May 2021 LM5002
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
STARTUP REGULATOR | |||||||
VVCC-REG | VCC regulator output | 6.55 | 6.85 | 7.15 | V | ||
VCC current limit | VVCC = 6 V | 15 | 20 | mA | |||
VCC UVLO threshold | VVCC increasing | 2.6 | 2.8 | 3 | V | ||
VCC undervoltage hysteresis | 0.1 | V | |||||
IIN | Bias current | VFB = 1.5 V | 3.1 | 4.5 | mA | ||
IQ | Shutdown current (IIN) | VEN = 0 V | 95 | 130 | µA | ||
EN THRESHOLDS | |||||||
EN shutdown threshold | VEN increasing | 0.25 | 0.45 | 0.65 | V | ||
EN shutdown hysteresis | 0.1 | V | |||||
EN standby threshold | VEN increasing | 1.2 | 1.26 | 1.32 | V | ||
EN standby hysteresis | 0.1 | V | |||||
EN current source | 6 | µA | |||||
MOSFET CHARACTERISTICS | |||||||
MOSFET RDS(ON) plus current sense resistance | ID = 0.25 A | 850 | 1600 | mΩ | |||
MOSFET leakage current | VSW = 75 V | 0.05 | 5 | µA | |||
MOSFET gate charge | VVCC = 6.9 V | 2.4 | nC | ||||
CURRENT LIMIT | |||||||
ILIM | Cycle by cycle current limit | 0.4 | 0.5 | 0.6 | A | ||
Cycle by cycle current limit delay | 100 | 200 | ns | ||||
OSCILLATOR | |||||||
FSW1 | Frequency1 | RRT = 48.7 kΩ | 225 | 260 | 295 | KHz | |
FSW2 | Frequency2 | RRT = 15.8 kΩ | 660 | 780 | 900 | KHz | |
VRT-SYNC | SYNC threshold | 2.2 | 2.6 | 3.2 | V | ||
SYNC pulse width minimum | VRT > VRT-SYNC + 0.5 V | 15 | ns | ||||
PWM COMPARATOR | |||||||
Maximum duty cycle | 80% | 85% | 90% | ||||
Minimum ON-time | VCOMP > VCOMP-OS | 25 | ns | ||||
Minimum ON-time | VCOMP < VCOMP-OS | 0 | ns | ||||
VCOMP-OS | COMP to PWM comparator offset | 0.9 | 1.3 | 1.55 | V | ||
ERROR AMPLIFIER | |||||||
VFB-REF | Feedback reference voltage | Internal reference and VFB = VCOMP | 1.241 | 1.26 | 1.279 | V | |
FB bias current | 10 | nA | |||||
DC gain | 72 | dB | |||||
COMP sink current | VCOMP = 250 mV | 2.5 | mA | ||||
COMP short circuit current | VFB = 0 V and VCOMP = 0 V | 0.9 | 1.2 | 1.5 | mA | ||
COMP open circuit voltage | VFB = 0 V | 4.8 | 5.5 | 6.2 | V | ||
COMP to SW delay | 42 | ns | |||||
Unity gain bandwidth | 3 | MHz | |||||
THERMAL SHUTDOWN | |||||||
TSD | Thermal shutdown threshold | 165 | °C | ||||
Thermal shutdown hysteresis | 20 | °C |