JAJSAQ4F January   2007  – May 2021 LM5002

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High Voltage VCC Regulator
      2. 7.3.2 Oscillator
      3. 7.3.3 External Synchronization
      4. 7.3.4 Enable and Standby
      5. 7.3.5 Error Amplifier and PWM Comparator
      6. 7.3.6 Current Amplifier and Slope Compensation
      7. 7.3.7 Power MOSFET
    4. 7.4 Device Functional Modes
      1. 7.4.1 Thermal Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VIN
      2. 8.1.2 SW PIN
      3. 8.1.3 EN or UVLO Voltage Divider Selection
      4. 8.1.4 Soft Start
    2. 8.2 Typical Applications
      1. 8.2.1 Non-Isolated Flyback Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Switching Frequency
          2. 8.2.1.2.2 Flyback Transformer
          3. 8.2.1.2.3 Peak MOSFET Current
          4. 8.2.1.2.4 Output Capacitance
          5. 8.2.1.2.5 Output Diode Rating
          6. 8.2.1.2.6 Power Stage Analysis
          7. 8.2.1.2.7 Loop Compensation
      2. 8.2.2 Isolated Flyback Regulator
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Boost Regulator
        1. 8.2.3.1 Design Requirements
      4. 8.2.4 24-V SEPIC Regulator
        1. 8.2.4.1 Design Requirements
      5. 8.2.5 12-V Automotive SEPIC Regulator
        1. 8.2.5.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Error Amplifier and PWM Comparator

An internal high-gain error amplifier generates an error signal proportional to the difference between the regulated output voltage and an internal precision reference. The output of the error amplifier is connected to the COMP pin allowing the user to add loop compensation, typically a Type-II network, as illustrated in Figure 7-1. This network creates a low-frequency pole that rolls off the high DC gain of the amplifier, which is necessary to accurately regulate the output voltage. FDC_POLE is the closed-loop unity gain (0 dB) frequency of this pole. A zero provides phase boost near the closed-loop unity gain frequency, and a high-frequency pole attenuates switching noise. The PWM comparator compares the current sense signal from the current sense amplifier to the error amplifier output voltage at the COMP pin.

Figure 7-1 Type II Compensator

When isolation between primary and secondary circuits is required, the Error Amplifier is usually disabled by connecting the FB pin to GND. This allows the COMP pin to be driven directly by the collector of an opto-coupler. In isolated designs the external error amplifier is placed on the secondary circuit and drives the opto-coupler LED. The compensation network is connected to the secondary side error amplifier. An example of an isolated regulator with an opto-coupler is shown in Figure 8-6.