JAJSOF6 April   2022 LM5013-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Control Architecture
      2. 7.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 7.3.3  Regulation Comparator
      4. 7.3.4  Internal Soft Start
      5. 7.3.5  On-Time Generator
      6. 7.3.6  Current Limit
      7. 7.3.7  N-Channel Buck Switch and Driver
      8. 7.3.8  Schottky Diode Selection
      9. 7.3.9  Enable/Undervoltage Lockout (EN/UVLO)
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Sleep Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Switching Frequency (RRON)
        3. 8.2.2.3 Buck Inductor (LO)
        4. 8.2.2.4 Schottky Diode (DSW)
        5. 8.2.2.5 Output Capacitor (COUT)
        6. 8.2.2.6 Input Capacitor (CIN)
        7. 8.2.2.7 Type 3 Ripple Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact PCB Layout for EMI Reduction
      2. 10.1.2 Feedback Resistors
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1.2 Feedback Resistors

Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.

Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node, the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high feedback resistances greater than 100 kΩ are used to set the output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This provides further shielding for the voltage feedback path from switching noise sources.