SNVS631D January   2010  – October 2016 LM5035C

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Voltage Start-Up Regulator
      2. 8.3.2  Line Undervoltage Detector
      3. 8.3.3  Line Overvoltage, Load Overvoltage, and Remote Thermal Protection
      4. 8.3.4  Reference
      5. 8.3.5  Cycle-by-Cycle Current Limit
      6. 8.3.6  Overload Protection Timer
      7. 8.3.7  Soft Start
      8. 8.3.8  PWM Comparator
      9. 8.3.9  Feedforward Ramp and Volt • Second Clamp
      10. 8.3.10 Oscillator, Sync Capability
      11. 8.3.11 Gate Driver Outputs (HO and LO)
      12. 8.3.12 Synchronous Rectifier Control Outputs (SR1 and SR2)
      13. 8.3.13 Thermal Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 VIN
        2. 9.2.2.2 For Applications >100 V
        3. 9.2.2.3 Current Sense
        4. 9.2.2.4 HO, HB, HS, and LO
        5. 9.2.2.5 Programmable Delay (DLY)
        6. 9.2.2.6 UVLO and OVP Voltage Divider Selection For R1, R2, and R3
        7. 9.2.2.7 Fault Protection
        8. 9.2.2.8 Hiccup Mode Current Limit Restart (RES)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PWP Package
20-Pin HTSSOP
Top View
LM5035C 30106802.gif
NHZ Package
24-Pin WQFN
Top View
LM5035C 30106803.gif

Pin Functions

PIN I/O DESCRIPTION APPLICATION INFORMATION
NAME HTSSOP WQFN
RAMP 1 23 I Modulator ramp signal An external RC circuit from VIN sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt • Second clamp comparator.
UVLO 2 24 I Line Undervoltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC and REF regulators are enabled. When UVLO reaches the 1.25-V threshold, the SS pin is released and the device enters the active mode. Hysteresis is set by an internal current sink that pulls 23 µA from the external resistor divider.
OVP 3 2 I Line Overvoltage Protection An external voltage divider from the power source sets the shutdown levels. The threshold is 1.25 V. Hysteresis is set by an internal current source that sources 23 µA into the external resistor divider.
COMP 4 3 I/O Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler detector.
RT 5 4 I Oscillator Frequency Control and Sync Clock Input. Normally biased at 2 V. An external resistor connected between RT and AGND sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor.
AGND 6 5 GND Analog Ground Connect directly to Power Ground.
CS 7 6 I Current Sense input for current limit If CS exceeds 0.25 V the output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 50 ns after HO or LO switches high to blank leading edge transients.
SS 8 7 I Soft-start Input An internal 110-µA current source charges an external capacitor to set the soft-start rate. During a current limit restart sequence, the internal current source is reduced to 1.2 µA to increase the delay before retry.
DLY 9 8 I Timing programming pin for the LO and HO to SR1 and SR2 outputs. An external resistor to ground sets the timing for the non-overlap time of HO to SR1 and LO to SR2.
RES 10 9 I Restart Timer If cycle-by-cycle current limit is exceeded during any cycle, a 22-µA current is sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V, the soft-start capacitor will be fully discharged and then released with a pullup current of 1.2 µA. After the first output pulse at LO (when SS > COMP offset, typically
1 V), the SS pin charging current will revert to 110 µA.
HB 11 11 I/O Boost voltage for the HO driver An external diode is required from VCC to HB and an external capacitor is required from HS to HB to power the HO gate driver.
HS 12 12 I/O Switch node Connection common to the transformer and both power switches. Provides a return path for the HO gate driver.
HO 13 13 O High-side gate drive output. Output of the high-side PWM gate driver. Capable of sinking 2-A peak current.
LO 14 14 O Low-side gate drive output. Output of the low-side PWM gate driver. Capable of sinking 2-A peak current.
PGND 15 15 GND Power Ground Connect directly to Analog Ground.
VCC 16 16 I/O Output of the high-voltage start-up regulator. The VCC voltage is regulated to 7.6 V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the start-up regulator will shut down, thus reducing the internal power dissipation.
SR2 17 17 O Synchronous rectifier driver output. Control output of the synchronous FET gate. Capable of 0.5-A peak current.
SR1 18 18 O Synchronous rectifier driver output. Control output of the synchronous FET gate. Capable of 0.5-A peak current.
REF 19 19 O Output of 5-V Reference Maximum output current is 20 mA. Locally decoupled with a 0.1-µF capacitor.
VIN 20 21 I Input voltage source Input to the start-up regulator. Operating input range is 13 V to 100 V with transient capability to 105 V. For power sources outside of this range, the LM5035C can be biased directly at VCC by an external regulator.
EP EP EP GND Exposed Pad, underside of package No electrical contact. Connect to system ground plane for reduced thermal resistance.
NC — 1 — No connection No electrical contact.
NC — 10 — No connection No electrical contact.
NC — 20 — No connection No electrical contact.
NC — 22 — No connection No electrical contact.