Figure 7-11 illustrates the half-bridge converter with low-side current sensing using a sense resistor.

Figure 7-11 Half-Bridge Converter with Low-Side Current Sensing

In LM5036 device, current limiting for the half-bridge converter is accomplished with three pins, including CS_SET, CS_POS and CS_ NEG pins, as shown in Figure 7-12. The current sense circuit limits positive current flowing from input to output and also negative current flowing from output to input. An input voltage compensation function helps to minimize the variation of effective output current limit across the range of input voltage. A pulse matching function is automatically implemented when the peak current limit circuit is active. This function matches the pulse width on the high and low primary FETs to maintain voltage balance of the half-bridge capacitor divider. This method ensures flux balance of the transformer during peak current limit operation.

Figure 7-12 Block Diagram of the Current Limiting Function

CS_SET pin is used to set the internal current limit threshold with an external resistor R_LIM according to Equation 7.

Equation 7.

where

• V_LIM (0.75-V typical) is the internal current limit setting voltage.

The CS_POS pin is driven by a signal representative of the current flowing through the low-side FET of the half-bridge converter. The current sense voltage at CS_POS pin (equal to CS_NEG pin voltage) is converted to a current sense signal through R₃ which is then sensed, scaled and compared against the internal current limit thresholds. In order to blank the leading-edge transient noise seen when the low-side FET is turned on, the current sense signal is blanked for t_CSBLK after LSG is turned on. If the magnitude of the noise spike is excessive, an additional filter capacitor C_F may be added to form an RC filter with R₁ to reduce the high-frequency noise spike. Both the leading-edge blanking and RC filter help to prevent false triggering of CBC current limiting operation.

In order to achieve bi-directional current sensing, an internal offset current (K_10a x I_{CS_SET}), is injected to the CS_POS pin. This offset allows positive internal thresholds on the CBC and NEG comparators that correspond to effective I_{CS_SET} and -I_{CS_SET} / 2 thresholds at the input.

When the current sense signal (I_R3 x 1 / K_10b) reaches the positive threshold (K_2a x I_{CS_SET}), CBC current limiting operation is activated. The controller essentially operates in peak current mode control, with the voltage loop open, during the CBC operation. A common issue with peak current mode control is sub-harmonic oscillation. This occurs when the effective duty cycle is greater than 50%. A common solution for sub-harmonic oscillation is to add slope compensation. The slope of the compensation ramp must be set to at least one half the downslope of the output inductor current transformed to the primary side across the current sense resistor. To eliminate sub-harmonic oscillation after one switching cycle, the slope compensation must be equal to the downslope of the output inductor current. This is known as deadbeat control. In LM5036, the slope compensation signal is a saw-tooth current signal ramping up from 0 to I_SLOPE at the oscillator frequency (twice the switching frequency of each primary FET).

However, another issue will arise after slope compensation is added. The current limit level varies with the input voltage, as illustrated in Figure 7-13. Because the slope compensation magnitude is different at different input voltages, the actual current limit level varies with input voltage for a given internal current limit threshold.

Figure 7-13 Current Sense and Current Limit Waveforms

A new feature, input voltage compensation, is provided by LM5036. By adding an extra signal, which is a function of input voltage, on top of the current sense signal and the slope compensation signal, variation of the current limit level can be minimized over the entire input voltage range. The CS_POS pin voltage at time t, after the rising edge of LSG, is expressed by Equation 8:

Equation 8.

Equation 9.

At the trip threshold, of the CBC comparator, both its inputs are at the same potential. In this case the voltage on the CS_NEG pin is expressed by Equation 10.

Equation 10.

Equation 11.

For a given duty cycle (D) the current sense threshold voltage that will just trigger the CBC comparator can be determined by combining Equation 9, Equation 10 and Equation 11.

Equation 12.

Now if we assume:

Equation 13.

Equation 12 simplifies to Equation 14.

Equation 14.

Section 8.2.2.11 gives an example design process for calculating the CBC external resistor values. The Excel Calculator Tool can also be used to assist in the process of selecting these resistor values.

LM5036 ensures flux balance of the main transformer during CBC operation. The duty cycles of the two primary FETs are always matched. If the low-side FET is terminated due to a current limit event, a matched duty cycle will be applied to the high-side FET during the next half switching period, regardless of the current condition. The matched duty cycles ensure voltage-second balance of the transformer which prevents transformer saturation.

The pulse matching operation is illustrated in Figure 7-14. When the current limit is reached during the low-side phase, a FLAG signal goes high. The RAMP signal is sampled at the rising edge of the FLAG signal and then held through the next half switching period for the high-side phase. When the high-side phase RAMP signal rises above the sampled value, the high-side PWM pulse is turned off so that the duty cycle are matched for both phases. In the meantime, the hiccup restart capacitor is charged with a current source I_RES-SRC1 (15-µA typical) during CBC operation. The pulse matching feature is handled automatically by the LM5036 controller and requires no action from the designer.

Figure 7-14 Pulse Matching Operation