The LM5036 device employs voltage-mode control with input voltage feed-forward for the main half-bridge converter. A simplified block diagram of the voltage-mode feedback control loop is shown in Figure 7-2.

Figure 7-2 Voltage-Mode Feedback Control Loop for Half-Bridge Converter

The output voltage (V_O) is sensed and compared against a reference voltage (V_REFSec) on the secondary side which produces an error voltage which is then processed by the error amplifier. The compensated error signal is transmitted across the isolation boundary through an opto-coupler and then gets injected into the COMP pin in the form of a control current. The COMP pin current is internally mirrored by a matching pair of NPN transistors which sink current through a 5-kΩ resistor connected to the 5-V internal reference. The resulting control voltage V_COMP is compared with the soft-start capacitor voltage (SS) and the smaller of the two passes through an offset V_SS-OS (1-V typical), followed by a 2:1 resistor divider before being applied to the PWM comparator to determine the duty cycle of the half-bridge converter. The PWM comparator polarity is configured such that with no current flowing into the COMP pin, the controller produces maximum duty cycle for the primary FETs.

An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is controlled by a current input, the voltage across the opto-coupler detector is nearly constant. The bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is thereby greatly reduced. Higher loop bandwidths can be realized because the bandwidth limiting pole associated with the opto-coupler is now at a much higher frequency.

The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator compares the modulation ramp signal at the RAMP pin to the COMP voltage to control the duty cycle. The modulation ramp signal can be implemented as a ramp proportional to the input voltage, known as feed-forward voltage mode control, as shown in Figure 7-3. The RAMP pin is reset by an internal MOSFET when RAMP voltage passes COMP voltage, current limit event, or at the conclusion of each PWM cycle, whichever comes earlier.

Slope proportional to input voltage (see Figure 7-4)

Figure 7-3 Feed-Forward Voltage-Mode Control Configuration

Figure 7-4 Modulation Ramp Slope

An external resistor (R_FF) and capacitor (C_FF) connected to VIN, AGND, and the RAMP pins are required to create a saw-tooth modulation ramp signal. The slope of the signal at RAMP will vary in proportion to the input voltage. The varying slope provides line feed-forward information necessary to improve line transient response with voltage-mode control. With a constant control signal, the on-time (t_ON) varies inversely with the input voltage (V_IN) to stabilize the volt-second product of the transformer. Using a line feed-forward ramp for PWM control requires very little change in the voltage regulation loop to compensate for changes in input voltage, as compared to a ramp with fixed slope. In addition, voltage-mode control is less susceptible to noise. Therefore, it is a good choice for wide input range power converter applications. However, voltage-mode control requires a Type-III compensation network due to the complex-conjugate poles of the L-C output filter.

Assistance with half-bridge voltage control loop design may be obtained using the Power Stage Designer™ tool.

The recommended capacitor value range for C_FF is from 100-pF to 1800-pF. Figure 7-3, shows that the C_FF value must be small enough to be discharged within the clock pulse-width (t_CLK). The value of R_FF required can be calculated from Equation 2

Equation 2.

For example, assuming a V_RAMP voltage of 1.5-V (a good compromise of signal range and noise immunity), V_IN(min) of 36-V, oscillator frequency of 400-kHz and C_FF = 560-pF results in R_FF = 105-kΩ.