JAJSID2F May   2011  – December 2019 LM5050-1 , LM5050-1-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      応用回路
      2.      代表的な冗長電源の構成
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM5050-1
    3. 6.3 ESD Ratings: LM5050-1-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IN, GATE, and OUT Pins
      2. 7.3.2 VS Pin
      3. 7.3.3 OFF Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 ON/OFF Control Mode
      2. 7.4.2 External Power Supply Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 MOSFET Selection
      2. 8.1.2 Short Circuit Failure of an Input Supply
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application With Input and Output Transient Protection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Power Supply Components (R1 C1,) Selection
          2. 8.2.1.2.2 MOSFET (Q1) Selection
          3. 8.2.1.2.3 D1 and D2 Selection for Inductive Kick-Back Protection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Using a Separate VS Supply for Low Vin Operation
      3. 8.2.3 ORing of Two Power Sources
      4. 8.2.4 Reverse Input Voltage Protection With IQ Reduction
      5. 8.2.5 Basic Application With Input Transient Protection
      6. 8.2.6 48-V Application With Reverse Input Voltage (VIN = –48 V) Protection
        1. 8.2.6.1 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.4 Reverse Input Voltage Protection With IQ Reduction

If Vs is powered while IN is floating or grounded, then about 0.5 mA will leak from the Vs pin into the IC and about 3 mA will leak from the OUT pin into the IC. From this leakage, about 50 uA will flow out of the IN pin and the rest will flow to ground. This does not affect long term reliability of the IC, but may influence circuit design.

In battery powered applications, whenever LM5050-1 functionality is not needed, the supply to the LM5050-1 can be disconnected by turning “OFF” Q2, as shown in Figure 29. This disconnects the ground path of the LM5050-1 and eliminates the current leakage from the battery.

The quiescent current of LM5050-1 can be also reduced by disconnecting the supply to VS pin, whenever LM5050-1 function is not need.

LM5050-1 LM5050-1-Q1 reverse_input_voltage_pro_snvs629.gifFigure 29. Reverse Input Voltage Protection With IQ Reduction Schematic