SNVS628H October   2009  – December 2019 LM5060

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Up Sequence
      2. 7.4.2 Status Conditions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Gate Control
      2. 8.1.2  Fault Timer
      3. 8.1.3  VGS Considerations
      4. 8.1.4  VDS Fault Condition
      5. 8.1.5  Overcurrent Fault
      6. 8.1.6  Restart After Overcurrent Fault Event
      7. 8.1.7  Enable
      8. 8.1.8  UVLO
      9. 8.1.9  OVP
      10. 8.1.10 Restart After OVP Event
      11. 8.1.11 nPGD Pin
    2. 8.2 Typical Applications
      1. 8.2.1 Example Number 1: LM5060EVAL Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VDS Fault Detection and Selecting Sense Pin Resistor RS
          2. 8.2.1.2.2 Turn-On Time
          3. 8.2.1.2.3 Fault Detection Delay Time
          4. 8.2.1.2.4 MOSFET Selection
          5. 8.2.1.2.5 Input and Output Capacitors
          6. 8.2.1.2.6 UVLO, OVP
          7. 8.2.1.2.7 POWER GOOD Indicator
          8. 8.2.1.2.8 Input Bypass Capacitor
          9. 8.2.1.2.9 Large Load Capacitance
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Example Number 2: Reverse Polarity Protection With Diodes
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curve
      3. 8.2.3 Example Number 3: Reverse Polarity Protection With Resistor
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Reverse Polarity Protection With a Resistor
          2. 8.2.3.2.2 Fault Detection With RS and RO
        3. 8.2.3.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View
LM5060 30104202.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 SENSE I Input voltage sense: a constant current sink (16 μA typical) at the SENSE pin flows through an external resistor to set the threshold for fault detection.
2 VIN P Supply voltage input: the operating voltage range is 5.5 V to 65 V. The internal power-on-reset (POR) circuit typically switches to the active state when the VIN pin is greater than 5.1 V. A small ceramic bypass capacitor close to this pin is recommended to suppress noise.
3 OVP I Over-voltage protection comparator input: an external resistor divider from the system input voltage sets the Over-Voltage turn-off threshold. The GATE pin is pulled low when OVP exceeds the typical 2.0-V threshold, but the controller is not latched off. Normal operation resumes when the OVP pin falls below typically 1.76 V.
4 UVLO I Under-voltage lock-out comparator input: the UVLO pin is used as an input under-voltage lock-out by connecting this pin to a resistor divider between input supply voltage and ground. The UVLO comparator is activated when EN is high. A voltage greater than typically 1.6 V at the UVLO pin will release the pull down devices on the GATE pin and allow the output to gradually rise. A constant current sink (5.5 µA typical) is provided to ensure the UVLO pin is low in an open circuit condition.
5 EN I Enable input: a voltage less than 0.8 V on the EN pin switches the LM5060 to a low current shutdown state. A voltage greater than 2.0 V on the EN pin enables the internal bias circuitry and the UVLO comparator. The GATE pin pull-up bias is enabled when both EN and UVLO are in the high state. A constant current sink (6 µA typical) is provided to ensure the EN pin is low in an open circuit condition.
6 GND – Circuit ground
7 TIMER I/O Timing capacitor: an external capacitor connected to this pin sets the VDS fault detection delay time. If the TIMER pin exceeds the 2.0-V threshold condition, the LM5060 will latch off the MOSFET and remain off until either the EN, UVLO or VIN (POR) input is toggled low and then high.
8 nPGD O Fault status: an open drain output. When the external MOSFET VDS decreases such that the OUT pin voltage exceeds the SENSE pin voltage, the nPGD indicator is active (low = no fault).
9 OUT I Output voltage sense: connect to the output rail (external MOSFET source). Internally used to detect VDS and VGS conditions.
10 GATE O Gate drive output: connect to the external MOSFET’s gate. A charge-pump driven constant current source (24 µA typical) charges the GATE pin. An internal zener clamps the GATE pin at typically 16.8 V above the OUT pin. The ΔV/Δt of the output voltage can be reduced by connecting a capacitor from the GATE pin to ground.
(1) I = Input, O = Output, P = Power