SNVS950C April   2014  – July 2016 LM5066I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SMBus Communications Timing Requirements and Definitions
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
      2. 8.3.2 Circuit Breaker
      3. 8.3.3 Power Limit
      4. 8.3.4 UVLO
      5. 8.3.5 OVLO
      6. 8.3.6 Power Good Pin
      7. 8.3.7 VDD Sub-Regulator
      8. 8.3.8 Remote Temperature Sensing
      9. 8.3.9 Damaged MOSFET Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up Sequence
      2. 8.4.2 Gate Control
      3. 8.4.3 Fault Timer and Restart
      4. 8.4.4 Shutdown Control
      5. 8.4.5 Enabling/Disabling and Resetting
    5. 8.5 Programming
      1. 8.5.1 PMBus Command Support
      2. 8.5.2 Standard PMBus Commands
        1. 8.5.2.1  OPERATION (01h)
        2. 8.5.2.2  CLEAR_FAULTS (03h)
        3. 8.5.2.3  CAPABILITY (19h)
        4. 8.5.2.4  VOUT_UV_WARN_LIMIT (43h)
        5. 8.5.2.5  OT_FAULT_LIMIT (4Fh)
        6. 8.5.2.6  OT_WARN_LIMIT (51h)
        7. 8.5.2.7  VIN_OV_WARN_LIMIT (57h)
        8. 8.5.2.8  VIN_UV_WARN_LIMIT (58h)
        9. 8.5.2.9  STATUS_BYTE (78h)
        10. 8.5.2.10 STATUS_WORD (79h)
        11. 8.5.2.11 STATUS_VOUT (7Ah)
        12. 8.5.2.12 STATUS_INPUT (7Ch)
        13. 8.5.2.13 STATUS_TEMPERATURE (7dh)
        14. 8.5.2.14 STATUS_CML (7Eh)
        15. 8.5.2.15 STATUS_OTHER (7Fh)
        16. 8.5.2.16 STATUS_MFR_SPECIFIC (80h)
        17. 8.5.2.17 READ_EIN (86h)
        18. 8.5.2.18 READ_VIN (88h)
        19. 8.5.2.19 READ_IIN (89h)
        20. 8.5.2.20 READ_VOUT (8Bh)
        21. 8.5.2.21 READ_TEMPERATURE_1 (8Dh)
        22. 8.5.2.22 READ_PIN (97h)
        23. 8.5.2.23 MFR_ID (99h)
        24. 8.5.2.24 MFR_MODEL (9Ah)
        25. 8.5.2.25 MFR_REVISION (9Bh)
      3. 8.5.3 Manufacturer Specific PMBus Commands
        1. 8.5.3.1  MFR_SPECIFIC_00: READ_VAUX (D0h)
        2. 8.5.3.2  MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
        3. 8.5.3.3  MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
        4. 8.5.3.4  MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
        5. 8.5.3.5  MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
        6. 8.5.3.6  MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
        7. 8.5.3.7  MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
        8. 8.5.3.8  MFR_SPECIFIC_07: GATE_MASK (D7h)
        9. 8.5.3.9  MFR_SPECIFIC_08: ALERT_MASK (D8h)
        10. 8.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
        11. 8.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)
        12. 8.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
        13. 8.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
        14. 8.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
        15. 8.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
        16. 8.5.3.16 MFR_SPECIFIC_14: READ_AVG_PIN (DFh)
        17. 8.5.3.17 MFR_SPECIFIC_15: READ_AVG_PIN
        18. 8.5.3.18 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
        19. 8.5.3.19 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
        20. 8.5.3.20 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
      4. 8.5.4 Reading and Writing Telemetry Data and Warning Thresholds
      5. 8.5.5 Determining Telemetry Coefficients Empirically With Linear Fit
      6. 8.5.6 Writing Telemetry Data
      7. 8.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)
      8. 8.5.8 SMBA Response
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 48-V, 10-A PMBus Hotswap Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design-In Procedure
          1. 9.2.1.2.1 Select RSNS and CL Setting
          2. 9.2.1.2.2 Selecting the Hotswap FETs
          3. 9.2.1.2.3 Select Power Limit
          4. 9.2.1.2.4 Set Fault Timer
          5. 9.2.1.2.5 Check MOSFET SOA
          6. 9.2.1.2.6 Set UVLO and OVLO Thresholds
            1. 9.2.1.2.6.1 Option A
            2. 9.2.1.2.6.2 Option B
            3. 9.2.1.2.6.3 Option C
            4. 9.2.1.2.6.4 Option D
          7. 9.2.1.2.7 Power Good Pin
          8. 9.2.1.2.8 Input and Output Protection
          9. 9.2.1.2.9 Final Schematic and Component Values
        3. 9.2.1.3 Application Curves
      2. 9.2.2 48-V, 20-A PMBus Hotswap Design
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1  Selecting the Sense Resistor and CL Setting
          2. 9.2.2.2.2  Selecting the Hotswap FETs
          3. 9.2.2.2.3  Select Power Limit
          4. 9.2.2.2.4  Set Fault Timer
          5. 9.2.2.2.5  Check MOSFET SOA
          6. 9.2.2.2.6  Switching to dv/dt-Based Start-Up
          7. 9.2.2.2.7  Choosing the VOUT Slew Rate
          8. 9.2.2.2.8  Select Power Limit and Fault Timer
          9. 9.2.2.2.9  Chose Input and Output Protection and Set Undervoltage, Overvoltage, and Power Good Thresholds
          10. 9.2.2.2.10 Final Schematic and Component Values
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

The following guidelines should be followed when designing the PC board for the LM5066I:

  1. Place the LM5066I close to the board’s input connector to minimize trace inductance from the connector to the MOSFET.
  2. Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066I to help minimize voltage transients which may occur on the input supply line. The TVS should be chosen such that the peak VIN is just lower the TVS reverse-bias voltage. Transients of 20 V or greater over the nominal input voltage can easily occur when the load current is shut off. A small capacitor may be sufficient for low current sense applications (I < 2 A). TI recommends to test the VIN input voltage transient performance of the circuit by current limiting or shorting the load and measuring the peak input voltage transient.
  3. Place a 1-µF ceramic capacitor as close as possible to VREF pin.
  4. Place a 1-µF ceramic capacitor as close as possible to VDD pin.
  5. The sense resistor (RSNS) should be placed close to the LM5066I. A trace should connect the VIN pad and Q1 pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RSNS using the Kelvin techniques as shown in Figure 52.
  6. The high current path from the board’s input to the load (through Q1), and the return path, should be parallel and close to each other to minimize loop inductance.
  7. The AGND and GND connections should be connected at the pins of the device. The ground connections for the various components around the LM5066I should be connected directly to each other, and to the LM5066I’s GND and AGND pin connection, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line.
  8. Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and turn-off.
  9. The board’s edge connector can be designed such that the LM5066I detects through the UVLO/EN pin that the board is being removed, and responds by turning off the load before the supply voltage is disconnected. For example, in Figure 51, the voltage at the UVLO/EN pin goes to ground before VIN is removed from the LM5066I as a result of the shorter edge connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM5066I’s VIN pin before the UVLO voltage is taken high, thereby allowing the LM5066I to turn on the output in a controlled fashion.

11.2 Layout Example

LM5066I CONN1.gif Figure 51. Recommended Board Connector Design
LM5066I 30115919.gif Figure 52. Sense Resistor Connections