SNVS950 Data sheet

SNVS950C April 2014 – July 2016 LM5066I

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PWP|28
- MPDS373B

サーマルパッド・メカニカル・データ

PWP|28
- PPTD290A

発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VIN, VIN_K, GATE, UVLO/EN, SENSE, PGD to GND ⁽²⁾	–0.3	100	V
	OVLO, FB, TIMER, PWR to GND	–0.3	7
	OUT to GND	–0.3	100
	SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND	–0.3	6
	SENSE to VIN_K, VIN to VIN_K, AGND to GND	–0.3	0.3
Junction temperature			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The GATE pin voltage is typically 13.6 V above VIN when the LM5066I is enabled. Therefore, the Absolute Maximum Rating for VIN applies only when the LM5066I is disabled, or for a momentary surge to that voltage because the Absolute Maximum Rating for the GATE pin is also 100 V.

7.2 ESD Ratings

			VALUE		UNIT
V_ESD ⁽¹⁾	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins except GATE⁽²⁾	± 2000		V
V_ESD ⁽¹⁾	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽³⁾	±500		V

(1) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2-kV rating for all pins except GATE which is rated for 1 kV.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
VIN, SENSE, OUT voltage		10		80	V
Junction temperature		–40		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5066I	UNIT
		PWP
		28 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	35.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽³⁾	19.9
R_θJB	Junction-to-board thermal resistance⁽⁴⁾	16.8
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	0.5
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	16.7
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁷⁾	2.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

Unless otherwise stated, the following conditions apply: V_VIN= 48 V, –40°C < T_J < 125°C, V_UVLO = 3 V , V_OVLO = 0 V, R_PWR= 20 kΩ. See ⁽¹⁾.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT (VIN PIN)
I_IN-EN	Input current, enabled	V_UVLO = 3 V and V_OVLO = 2 V		5.6	7	mA
POR_IT	Power-on reset threshold at V_VIN to trigger insertion timer	V_VIN increasing		7.8	9.0	V
POR_EN	Power-on reset threshold at V_VIN to enable all functions	V_VIN increasing		8.6	9.9	V
POR_HYS	POR_EN hysteresis	V_VIN decreasing		100		mV
VDD REGULATOR (VDD PIN)
V_DD		I_VDD = 0 mA	4.60	4.90	5.15	V
V_DD		I_VDD = 10 mA	4.60	4.85	5.15	V
V_DDILIM	V_VDD current limit		–50	–30	–15	mA
V_DDPOR	V_VDD voltage reset threshold	V_VDD rising		4.1		V
UVLO/EN, OVLO PINS
UVLO_TH	UVLO threshold	V_UVLO falling	2.41	2.48	2.55	V
UVLO_HYS	UVLO hysteresis current	V_UVLO = 1 V	16	20	24	µA
UVLO_BIAS	UVLO bias current	V_UVLO = 3 V			1	µA
OVLO_TH	OVLO threshold	V_OVLO rising	2.39	2.46	2.53	V
OVLO_HYS	OVLO hysteresis current	V_OVLO= 1 V	–24	–21	–16	µA
OVLO_BIAS	OVLO bias current	V_OVLO = 1 V			1	µA
POWER GOOD (PGD PIN)
PGD_VOL	Output low voltage	I_SINK = 2 mA		100	400	mV
PGD_IOH	Off leakage current	V_PGD= 80 V			1	µA
FB PIN
FB_TH	FB threshold	V_UVLO = 3 V and V_OVLO = 2 V	2.41	2.46	2.52	V
FB_HYS	FB hysteresis current		–25	–20	–15	µA
FB_LEAK	Off leakage current	V_FB = 2.3 V			1	µA
POWER LIMIT (PWR PIN)
	Power limit sense voltage (V_{VIN_K} – V_SENSE)	V_SENSE – V_OUT = 48 V, R_PWR = 60 kΩ	7.4	9.4	11.4	mV
		V_SENSE – V_OUT = 48 V, R_PWR = 20 kΩ	1.5	3.5	5.7	mV
		V_SENSE – V_OUT = 48 V, R_PWR = 20 kΩ, T_J = 0°C to 85°C	1.85	3.5	5.02	mV
		V_SENSE – V_OUT = 24 V, R_PWR = 60 kΩ	15	18.75	22.5	mV
		V_SENSE – V_OUT = 24 V, R_PWR = 20 kΩ	5	7.23	10	mV
I_PWR	PWR pin current	V_PWR = 2.5 V		-20		µA
R_SAT(PWR)	PWR pin impedance when disabled	V_UVLO = 2 V		120		Ω
GATE CONTROL (GATE PIN)
I_GATE	Source current	Normal operation	–40	–20	–7.5	µA
	Fault sink current	V_UVLO = 2 V	3.4	4.2	5.3	mA
	POR circuit breaker sink current	V_{VIN_K} – V_SENSE = 60 mV or V_VIN < POR_IT, V_GATE = 5 V, OUT = 0 V, CB/CL ratio bit = 0, CL = 1	90	160	230	mA
V_GATEZ	Reverse-bias voltage of GATE to OUT Zener diode, I_Z = –100 µA	V_GATE– V_OUT	12	16.5	18	V
V_GATECP	Peak charge pump voltage in normal operation (V_IN = V_OUT)	V_GATE– V_OUT	11	13	15	V
OUT PIN
I_OUT-EN	OUT bias current, enabled	V_IN = V_OUT, normal operation	60	80	100	µA
I_OUT-DIS	OUT bias current, disabled ⁽²⁾	Disabled, OUT = 0 V, V_{VIN_K} = V_SENSE	–65	–50	–35	µA
CURRENT LIMIT
V_CL	Current limit threshold voltage (V_{VIN_K} – V_SENSE)	CL = VDD	23.4	26	28.6	mV
V_CL	Current limit threshold voltage (V_{VIN_K} – V_SENSE)	CL = GND	45	50	55	mV
I_SENSE	SENSE input current	Enabled, SENSE = OUT	20	25	35	µA
		Disabled, OUT = 0 V		66
		Enabled, OUT = 0 V	190	220	250
CIRCUIT BREAKER
RT_CB	Circuit breaker to current limit ratio: (V_{VIN_K} – V_SENSE)_CB/V_CL	CB/CL ratio bit = 0, ILIM = 50 mV	1.64	1.94	2.23	V/V
		CB/CL ratio bit = 1, ILIM = 50 mV	3.28	3.87	4.45
		CB/CL ratio bit = 0, ILIM = 26 mV	1.5	1.88	2.3
		CB/CL ratio bit = 1, ILIM = 26 mV	3.1	3.75	4.45
V_CB	Circuit breaker threshold voltage: (V_{VIN_K} – V_SENSE)	CB/CL ratio bit = 0, ILIM = 50 mV	76	96	116	mV
		CB/CL ratio bit = 1, ILIM = 50 mV	155	193	235
		CB/CL ratio bit = 0, ILIM = 26 mV	38	48	58
		CB/CL ratio bit = 1, ILIM = 26 mV	76	96	116
TIMER (TIMER PIN)
V_TMRH	Upper threshold		3.74	3.9	4.07	V
V_TMRL	Lower threshold	Restart cycles	1	1.2	1.4	V
V_TMRL	Lower threshold	End of eighth cycle re-enable threshold		0.3		V
I_TIMER	Insertion time current	TIMER pin = 2 V	–5.9	–4.8	–3.3	µA
	Sink current, end of insertion time		0.9	1.5	2.1	mA
	Fault detection current		–90	–75	–60	µA
	Fault sink current		1.7	2.5	3.2	µA
DC_FAULT	Fault restart duty cycle			0.5%
INTERNAL REFERENCE
V_REF	Reference voltage		2.93	2.97	3.02	V
ADC AND MUX
	Resolution			12		Bits
INL	Integral non-linearity	ADC only		±4		LSB
t_ACQUIRE	Acquisition + conversion time	Any channel		100		µs
t_RR	Acquisition round robin time	Cycle all channels		1		ms
TELEMETRY ACCURACY
I_INFSR	Current input full-scale range	CL = GND	50	54.4	58	mV
I_INFSR	Current input full-scale range	CL = VDD	26	27.0	29	mV
I_INLSB	Current input LSB	CL = GND		13.30		µV
I_INLSB	Current input LSB	CL = VDD		6.70		µV
V_AUXFSR	VAUX input full-scale range		2.93	2.97	3.01	V
V_AUXLSB	VAUX input LSB			725		µV
V_INFSR	Input voltage full-scale range		86	88.9	91	V
V_INLSB	Input voltage LSB			21.7		mV
V_OUTFSR	Output voltage full-scale range		86	88.9	91	V
V_OUTLSB	Output voltage LSB			21.7		mV
I_INACC	Input current absolute accuracy	V_{VIN_K} – V_SENSE = 22 mV (80% I_INFSR), CL = VDD	–1.75	%	+1.75
		V_{VIN_K} – V_SENSE = 5 mV (19% I_INFSR), CL = VDD	–6.0	%	+6.0
		V_{VIN_K} – V_SENSE = 44 mV (80% I_INFSR), CL = GND	–3.5	%	+3.5
V_ACC	VIN, VOUT absolute accuracy	V_VIN, V_VOUT = 48, 80 V	–1.25	%	+1.25
	VIN, VOUT absolute accuracy	V_VIN, V_VOUT = 10 V	–2.5	%	+2.5
	VAUX absolute accuracy	V_AUX = 2.8 V	–1.25	%	+1.25
P_INACC	Input power accuracy	V_VIN = 48 V, V_{VIN_K} – V_SENSE = 22 mV (80% I_INFSR), CL = VDD	–2.5	%	+2.5
		V_VIN = 48 V, V_{VIN_K} – V_SENSE = 5 mV (19% I_INFSR), CL = VDD	–6.5	%	+6.5
		V_VIN = 48V , V_{VIN_K} – V_SENSE= 44 mV (80% I_INFSR), CL = GND	–4.5	%	+4.5
REMOTE DIODE TEMPERATURE SENSOR
T_ACC	Temperature accuracy using local diode	T_A = 25°C to 85°C		2	10	°C
T_ACC	Remote diode resolution			9		bits
I_DIODE	External diode current source	High level		250	325	µA
I_DIODE	External diode current source	Low level		9.4		µA
	Diode current ratio			25.9		µA
PMBus PIN THRESHOLDS (SMBA, SDA, SCL)
V_IL	Data, clock input low voltage				0.9	V
V_IH	Data, clock input high voltage		2.1		5.5	V
V_OL	Data output low voltage	I_SINK = 3 mA	0		0.4	V
I_LEAK	Input leakage current	SDAI,SMBA,SCL = 5 V			1	µA
CONFIGURATION PIN THRESHOLDS (CL, RETRY)
V_IH	Threshold voltage		3			V
I_LEAK	Input leakage current	CL, RETRY = 5 V		5		µA

(1) Current out of a pin is indicated as a negative value.

(2) OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.

7.6 SMBus Communications Timing Requirements and Definitions

PARAMETER		MIN	MAX	UNIT
ƒ_SMB	SMBus operating frequency	10	400	kHz
t_BUF	Bus free time between stop and start condition	1.3		µs
t_HD:STA	Hold time after (repeated) start condition. After this period, the first clock is generated.	0.6		µs
t_SU:STA	Repeated start condition setup time	0.6		µs
t_SU:STO	Stop condition setup time	0.6		µs
t_HD:DAT	Data hold time	85		ns
t_SU:DAT	Data setup time	100		ns
t_TIMEOUT	Clock low time-out⁽¹⁾	25	35	ms
t_LOW	Clock low period	1.5		µs
t_HIGH	Clock high period⁽²⁾	0.6		µs
t_LOW:SEXT	Cumulative clock low extend time (slave device)⁽³⁾		25	ms
t_LOW:MEXT	Cumulative low extend time (master device)⁽⁴⁾		10	ms
t_F	Clock or data fall time⁽⁵⁾	20	300	ns
t_R	Clock or data rise time⁽⁵⁾	20	300	ns

(1) Devices participating in a transfer will timeout when any clock low exceeds the value of t_TIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than t_TIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).

(2) t_{HIGH MAX} provides a simple method for devices to detect bus idle conditions.

(3) t_LOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself.

(4) t_LOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop.

(5) Rise and fall time is defined as follows: t_R = ( V_ILMAX – 0.15) to (V_IHMIN + 0.15); t_F = 0.9 VDD to (V_ILMAX – 0.15)

Figure 1. SMBus Timing Diagram

7.7 Switching Characteristics

Unless otherwise stated, the following conditions apply: V_VIN= 48 V, –40°C < T_J < 125°C, V_UVLO = 3 V , V_OVLO = 0 V, R_PWR= 20 kΩ.

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
UVLO/EN, OVLO PINS
UVLO_DEL	UVLO delay	Delay to GATE high	7	9.6	12.2	µs
UVLO_DEL	UVLO delay	Delay to GATE low	6	8.5	11	µs
OVLO_DEL	OVLO delay	Delay to GATE high	7	9.6	12.2	µs
OVLO_DEL	OVLO delay	Delay to GATE low	6	8.5	11	µs
FB PIN
FB_DEL	FB Delay	Delay to PGD high	5	7.6	10	µs
FB_DEL	FB Delay	Delay to PGD low	7	9.2	12.5	µs
CURRENT LIMIT
t_CL	Response time	VIN-SENSE stepped from 0 to 80 mV; CL = GND		30	50	µs
CIRCUIT BREAKER
t_CB	Response time	VIN-SENSE stepped from 0 to 150 mV, time to GATE low, no load		0.36	0.8	µs
TIMER (TIMER PIN)
t_{FAULT_DELAY}	Fault to GATE low delay	TIMER pin reaches the upper threshold		12		µs

7.8 Typical Characteristics

Unless otherwise specified, the following conditions apply: T_J = 25°C, V_IN = 48 V. All graphs show junction temperature.

	SPACE

Figure 2. Input Current vs VIN and T_J

Figure 4. Gate Sourcing Current vs T_J

POR event or CB triggered

Figure 6. Gate Sinking Current vs T_J

Inject 100 µA into gate node. Measure GATE-SOURCE

Figure 8. Gate Clamping Voltage vs T_J

Figure 10. OVLO Threshold vs T_J

Figure 12. Current Limit Threshold vs T_J

	Device Enabled

Figure 3. Sense Current vs VOUT and T_J

Figure 5. Gate Sinking Current vs T_J

	SPACE

Figure 7. Gate Voltage vs T_J

	SPACE

Figure 9. UVLO/EN Threshold vs T_J

Figure 11. Power Good Feedback Threshold vs T_J