The LM5121 is a synchronous boost controller intended for high-efficiency, high-power boost regulator applications. The control method is based upon peak current mode control. Current mode control provides inherent line feed-forward, cycle-by-cycle current limiting and ease of loop compensation.
The switching frequency is programmable up to 1 MHz. Higher efficiency is achieved using two robust N-channel MOSFET gate drivers with adaptive dead-time control. A user-selectable diode emulation mode enables discontinuous mode operation for improved efficiency at light load conditions.
The LM5121 provides disconnection switch control which completely disconnects the output from the input during an output short or a shutdown condition. During start-up sequence, inrush current is limited by the disconnection switch control.
An internal charge pump allows 100% duty cycle operation of the high-side synchronous switch (Bypass operation). Additional features include thermal shutdown, frequency synchronization, hiccup mode current limit and adjustable line undervoltage lockout.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LM5121 | HTSSOP (20) | 6.50 mm x 4.40 mm |
LM5121-Q1 |
Changes from B Revision (December 2014) to C Revision
Changes from A Revision (September 2013) to B Revision
PIN | I/O(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 9 | G | Analog ground connection. Return for the internal voltage reference and analog circuits. |
BST | 20 | P/I | High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side N-channel MOSFET gate and should be placed as close to controller as possible. An internal BST charge pump will supply 200 µA current into bootstrap capacitor for bypass operation. |
COMP | 11 | O | Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin. |
CSN | 3 | I | Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor. |
CSP | 4 | I | Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense resistor. |
DG | 2 | O | Disconnection switch control pin. Connect to the gate terminal of the N-channel MOSFET disconnection switch. |
DS | 1 | I/O | Source connection of N-channel MOSFET disconnection switch. Connect to the source terminal of the disconnection switch, the cathode terminal of the freewheeling diode and the supply input of boost inductor. |
EP | EP | N/A | Exposed pad of the package. No internal electrical connections. Should be soldered to the large ground plane to reduce thermal resistance. |
FB | 10 | I | Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 1.2 V. |
HO | 19 | O | High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous N-channel MOSFET switch through a short, low inductance path. |
LO | 16 | O | Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel MOSFET switch through a short, low inductance path. |
MODE | 13 | I | Switching mode selection pin. Internal 700 kΩ pull-up and 100 kΩ pull-down resistor hold MODE pin to 0.15 V as a default. By adding external pull-up or pull-down resistor, MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2 V, diode emulation mode threshold, forced PWM mode is enabled, allowing current to flow in either direction through the high-side N-channel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode. Skip cycle comparator is activated as a default condition when the MODE pin is left floating. If the MODE pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load. |
PGND | 15 | G | Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the source terminal of the low-side N-channel MOSFET switch. |
RES | 14 | O | The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay during over load conditions and hiccup mode short circuit protection. Connect directly to the AGND when hiccup mode operation is not required. |
SLOPE | 12 | I | Slope compensation is programmed by an external resistor between SLOPE and the AGND. |
SS | 7 | I | Soft-start programming pin. An external capacitor and an internal 10 μA current source set the ramp rate of the internal error amplifier reference during soft-start. |
SW | 18 | I/O | Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET switch through short, low inductance paths. |
SYNCIN/RT | 8 | I | The internal oscillator frequency is programmed by an external resistor between RT and the AGND. The internal oscillator can be synchronized to an external clock by applying a positive pulse signal into this pin. The recommended maximum internal oscillator frequency is 2 MHz which leads to 1 MHz maximum switching frequency. |
UVLO | 6 | I | Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10 μA current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external UVLO resistors to provide hysteresis. The UVLO pin should not be left floating. |
VCC | 17 | P/O/I | VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller as possible. |
VIN | 5 | P/I | Supply voltage input source for the VCC regulator. Connect to the input capacitor and source power supply connection with short, low impedance paths. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input | VIN, CSP, CSN | –0.3 | 75 | V |
BST to SW, FB, MODE, UVLO, VCC(2) | –0.3 | 15 | ||
SW | –5.0 | 105 | ||
BST | –0.3 | 115 | ||
SS, SLOPE, SYNCIN/RT | –0.3 | 7 | ||
CSP to CSN, PGND | –0.3 | 0.3 | ||
Output(3) | DG to DS | –3.0 | 18 | |
DG to VIN | –75 | 15 | ||
DS | –3.0 | 75 | ||
HO to SW | –0.3 | BST to SW+0.3 | ||
LO | –0.3 | VCC+0.3 | ||
COMP, RES | –0.3 | 7 | ||
Thermal | Junction Temperature | –40 | 150 | ºC |
Tstg | Storage temperature range | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2 | kV |
Charged device model (CDM), per JEDED specification JESD22-C101 (2) | ±1 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2 | kV | |
Charged device model (CDM), per AEC Q100-011 | Corner pins | ±1 | |||
Other pins |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Input supply voltage(2) | VIN | 4.5 | 65 | V | |
Disconnection switch voltage(2) | DG, DS | 3.0 | 65 | ||
Low-side driver bias voltage | VCC | 14 | |||
High-side driver bias voltage | BST to SW | 3.8 | 14 | ||
Current sense common mode range(2) | CSP, CSN | 3.0 | 65 | ||
Switch node voltage | SW | 100 | |||
Junction temperature | TJ | –40 | 125 | ºC |
THERMAL METRIC(1) | LM5121, LM5121-Q1 |
UNIT | ||
---|---|---|---|---|
PWP (HTSSOP) | ||||
20 PINS | ||||
RθJA | Junction-to-ambient thermal resistance (Typ.) | 40 | ºC/W | |
RθJC(bot) | Junction-to-case (bot) thermal resistance (Typ.) | 4 | ºC/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN SUPPLY | |||||||
ISHUTDOWN | VIN shutdown current | VUVLO = 0 V | 9 | 17 | µA | ||
IBIAS | VIN operating current (exclude the current into RT resistor) | VUVLO = 2 V, non-switching | 4 | 5 | mA | ||
VCC REGULATOR | |||||||
VCC(REG) | VCC regulation | No load | 6.9 | 7.6 | 8.3 | V | |
VCC dropout (VIN to VCC) | VVIN = 4.5 V, no external load | 0.25 | |||||
VVIN = 4.5 V, IVCC = 25 mA | 0.28 | 0.5 | |||||
VCC sourcing current limit | VVCC = 0 V | 50 | 62 | mA | |||
IVCC | VCC operating current (exclude the current into RT resistor) | VVCC = 8.3 V | 3.5 | 5 | |||
VVCC = 12 V | 4.5 | 8 | |||||
VCC undervoltage threshold | VCC rising, VVIN = 4.5 V | 3.9 | 4.0 | 4.1 | V | ||
VCC falling, VVIN = 4.5 V | 3.7 | ||||||
VCC undervoltage hysteresis | 0.385 | ||||||
UNDERVOLTAGE LOCKOUT | |||||||
UVLO threshold | UVLO rising | 1.17 | 1.20 | 1.23 | V | ||
UVLO hysteresis current | VUVLO = 1.4 V | 7 | 10 | 13 | µA | ||
UVLO standby threshold | UVLO rising | 0.3 | 0.4 | 0.5 | V | ||
UVLO standby hysteresis | 0.1 | 0.125 | |||||
MODE | |||||||
Diode emulation mode threshold | MODE rising | 1.20 | 1.24 | 1.28 | V | ||
Diode emulation mode hysteresis | 0.1 | ||||||
Default MODE voltage | 145 | 155 | 170 | mV | |||
Default skip cycle threshold | COMP rising, measured at COMP | 1.290 | V | ||||
COMP falling, measured at COMP | 1.245 | ||||||
Skip cycle hysteresis | Measured at COMP | 40 | mV | ||||
ERROR AMPLIFIER | |||||||
VREF | FB reference voltage | Measured at FB, VFB= VCOMP | 1.188 | 1.200 | 1.212 | V | |
FB input bias current | VFB= VREF | 5 | nA | ||||
VOH | COMP output high voltage | ISOURCE = 2 mA, VVCC = 4.5 V | 2.75 | V | |||
ISOURCE = 2 mA, VVCC = 12 V | 3.40 | ||||||
VOL | COMP output low voltage | ISINK = 2 mA | 0.25 | ||||
AOL | DC gain | 80 | dB | ||||
fBW | Unity gain bandwidth | 3 | MHz | ||||
OSCILLATOR | |||||||
fSW1 | Switching frequency 1 | RT = 20 kΩ | 400 | 450 | 500 | kHz | |
fSW2 | Switching frequency 2 | RT = 10 kΩ | 775 | 875 | 975 | ||
RT output voltage | 1.2 | V | |||||
RT sync rising threshold | RT rising | 2.5 | 2.9 | ||||
RT sync falling threshold | RT falling | 1.6 | 2.0 | ||||
Minimum sync pulse width | 100 | ns | |||||
DISCONNECTION SWITCH CONTROL | |||||||
IDIS-SOURCE | DG current source | UVLO = 2 V, Sourcing | 25 | uA | |||
IDIS-SINK | DG current sink | Inrush Control, Sinking | 67 | ||||
DG discharge switch RDS-ON | Circuit Breaker | 38 | Ω | ||||
DG charge pump regulation | DG to VIN, No load, VVIN = 4.5 V | 9.5 | 10.5 | 11.5 | V | ||
DG to VIN, No load, VVIN = 12 V | 12.5 | ||||||
VGS-DET | VGS detection threshold | DG to DS, Rising, VVIN = 12 V | 4.0 | 5.4 | 6.5 | ||
VGS detection hysteresis | 0.2 | ||||||
Transconductance gain | CSP to CSN to IDG | 12 | uA/mV | ||||
SLOPE COMPENSATION | |||||||
SLOPE output voltage | 1.17 | 1.20 | 1.23 | V | |||
VSLOPE | Slope compensation amplitude | RSLOPE = 20 kΩ, fSW = 100 kHz, 50% duty cycle, TJ = –40ºC to +125ºC | 1.375 | 1.650 | 1.925 | ||
RSLOPE= 20 kΩ, fSW= 100 kHz, 50% duty cycle, TJ = 25ºC | 1.400 | 1.650 | 1.900 | ||||
SOFT-START | |||||||
ISS-SOURCE | SS current source | VSS = 0 V | 7.5 | 10 | 12 | µA | |
SS discharge switch RDS-ON | 13 | Ω | |||||
PWM COMPARATOR | |||||||
tLO-OFF | Forced LO off-time | VVCC = 5.5 V | 420 | 550 | ns | ||
VVCC = 4.5 V | 360 | 500 | |||||
tON-MIN | Minimum LO on-time | RSLOPE = 20 kΩ | 150 | ||||
RSLOPE = 200 kΩ | 300 | ||||||
COMP to PWM voltage drop | TJ = –40ºC to +125ºC | 0.95 | 1.10 | 1.25 | V | ||
TJ = 25ºC | 1.00 | 1.10 | 1.20 | ||||
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT | |||||||
VCS-TH1 | Cycle-by-cycle current limit threshold | CSP to CSN, TJ = –40ºC to +125ºC | 65.5 | 75.0 | 87.5 | mV | |
CSP to CSN, TJ = 25ºC | 67.0 | 75.0 | 86.0 | ||||
VCS-TH2 –VCS-TH1 | 5 | ||||||
VCS-TH2 | Inrush current limit threshold | CSP to CSN | 80 | 110 | 133 | ||
VCS-TH3 | Circuit breaker enable threshold | CSP to CSN, Rising | 143 | 160 | 170 | ||
VCS-TH3 – VCS-TH2 | 20 | ||||||
VCS-TH4 | Circuit breaker disable threshold | CSP to CSN, Falling | 4.0 | 11.5 | 16.0 | ||
VCS-ZCD | Zero cross detection threshold | CSP to CSN, Rising | 7 | ||||
CSP to CSN, Falling | 0.3 | 6 | 12 | ||||
Current sense amplifier gain | 10 | V/V | |||||
ICSP | CSP input bias current | 12 | µA | ||||
ICSN | CSN input bias current | 11 | |||||
Bias current matching | ICSP to ICSN | –1.75 | 1 | 3.75 | |||
CS to LO delay | Current sense / current limit delay | 150 | ns | ||||
HICCUP MODE RESTART | |||||||
VRES | Restart threshold | RES rising | 1.15 | 1.20 | 1.25 | V | |
VHCP-UPPER | Hiccup counter upper threshold | RES rising | 4.2 | ||||
RES rising, VVIN = VVCC = 4.5 V | 3.6 | ||||||
VHCP-LOWER | Hiccup counter lower threshold | RES falling | 2.15 | ||||
RES falling, VVIN = VVCC = 4.5 V | 1.85 | ||||||
IRES-SOURCE1 | RES current source1 | Fault-state charging current | 20 | 30 | 40 | µA | |
IRES-SINK1 | RES current sink1 | Normal-state discharging current | 5 | ||||
IRES-SOURCE2 | RES current source2 | Hiccup mode off-time charging current | 10 | ||||
IRES-SINK2 | RES current sink2 | Hiccup mode off-time discharging current | 5 | ||||
Hiccup cycle | 8 | Cycles | |||||
RES discharge switch RDS-ON | 40 | Ω | |||||
Ratio of hiccup mode off-time to restart delay time | 122 | ||||||
HO GATE DRIVER | |||||||
VOHH | HO high-state voltage drop | IHO = –100 mA, VOHH = VBST – VHO | 0.15 | 0.24 | V | ||
VOLH | HO low-state voltage drop | IHO = 100 mA, VOLH = VHO – VSW | 0.1 | 0.18 | |||
HO rise time (10% to 90%) | CLOAD = 4700 pF, VBST = 12 V | 25 | ns | ||||
HO fall time (90% to 10%) | CLOAD = 4700 pF, VBST = 12 V | 20 | |||||
IOHH | Peak HO source current | VHO = 0 V, VSW = 0 V, VBST = 4.5 V | 0.8 | A | |||
VHO = 0 V, VSW = 0 V, VBST = 7.6 V | 1.9 | ||||||
IOLH | Peak HO sink current | VHO = VBST = 4.5 V | 1.9 | ||||
VHO = VBST = 7.6 V | 3.2 | ||||||
IBST | BST charge pump sourcing current | VVIN = VSW = 9.0 V , VBST - VSW = 5.0 V | 90 | 200 | µA | ||
BST charge pump regulation | BST to SW, IBST= –70 μA, VVIN = VSW = 9.0 V |
5.3 | 6.2 | 6.75 | V | ||
BST to SW, IBST = –70 μA, VVIN = VSW = 12 V |
7 | 8.5 | 9 | ||||
BST to SW undervoltage | 2.0 | 3.0 | 3.5 | ||||
BST DC bias current | VBST - VSW = 12 V, VSW = 0 V | 30 | 45 | µA | |||
LO GATE DRIVER | |||||||
VOHL | LO high-state voltage drop | ILO = –100 mA, VOHL = VVCC – VLO | 0.15 | 0.25 | V | ||
VOLL | LO low-state voltage drop | ILO = 100 mA, VOLL = VLO | 0.1 | 0.17 | |||
LO rise time (10% to 90%) | CLOAD = 4700 pF | 25 | ns | ||||
LO fall time (90% to 10%) | CLOAD = 4700 pF | 20 | |||||
IOHL | Peak LO source current | VLO = 0 V, VVCC = 4.5 V | 0.8 | A | |||
VLO = 0 V | 2.0 | ||||||
IOLL | Peak LO sink current | VLO = VVCC = 4.5 V | 1.8 | ||||
VLO = VVCC | 3.2 | ||||||
SWITCHING CHARACTERISTICS | |||||||
tDLH | LO fall to HO rise delay | No load, 50% to 50% | 50 | 80 | 115 | ns | |
tDHL | HO fall to LO rise delay | No load, 50% to 50% | 60 | 80 | 105 | ||
THERMAL | |||||||
TSD | Thermal shutdown | Temperature rising | 165 | ºC | |||
Thermal shutdown hysteresis | 25 |