LM5121/-Q1 Wide Input Synchronous Boost Controller with Disconnection Switch Control

1 Features

AEC-Q100 Qualified with the following results:
- Device Temperature Grade 1: -40°C to +125°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level 2
- Device CDM ESD Classification Level C6
Maximum Input Voltage: 65 V
Min Input Voltage: 3.0 V (4.5 V for startup)
Output Voltage Up to 100 V
Bypass (V_OUT = V_IN) Operation
1.2-V Reference with ±1.0% Accuracy
Free-Run/Synchronizable up to 1 MHz
Peak Current Mode Control
Robust Integrated 3-A Gate Drivers
Adaptive Dead-Time Control
Optional Diode Emulation Mode
Programmable Cycle-by-Cycle Current Limit
Programmable Line UVLO
Programmable Soft-Start
Thermal Shutdown Protection
Low Shutdown Quiescent Current: 9 μA
Programmable Slope Compensation
Programmable Skip Cycle Mode Reduces Standby Power
Supports External VCC Bias Supply Option
Load Disconnection in Shutdown Mode (True Shutdown)
Inrush Current Limiting
Hiccup Mode Short Circuit/Overload Protection
Circuit Breaker Function
Capable of Input Transient Suppression
Capable of Reverse Battery Protection
Thermally Enhanced 20-Pin HTSSOP

2 Applications

12-V, 24-V, and 48-V Power Systems
Automotive Start-Stop
High Current Boost Power Supply
Battery Powered System

3 Description

The LM5121 is a synchronous boost controller intended for high-efficiency, high-power boost regulator applications. The control method is based upon peak current mode control. Current mode control provides inherent line feed-forward, cycle-by-cycle current limiting and ease of loop compensation.

The switching frequency is programmable up to 1 MHz. Higher efficiency is achieved using two robust N-channel MOSFET gate drivers with adaptive dead-time control. A user-selectable diode emulation mode enables discontinuous mode operation for improved efficiency at light load conditions.

The LM5121 provides disconnection switch control which completely disconnects the output from the input during an output short or a shutdown condition. During start-up sequence, inrush current is limited by the disconnection switch control.

An internal charge pump allows 100% duty cycle operation of the high-side synchronous switch (Bypass operation). Additional features include thermal shutdown, frequency synchronization, hiccup mode current limit and adjustable line undervoltage lockout.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LM5121	HTSSOP (20)	6.50 mm x 4.40 mm
LM5121-Q1	HTSSOP (20)	6.50 mm x 4.40 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Application Diagram

4 Revision History

Changes from B Revision (December 2014) to C Revision

Added Automotive ESD FeaturesGo
Changed equation Go

Changes from A Revision (September 2013) to B Revision

Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

HTSSOP

PWP Package

TOP VIEW

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
AGND	9	G	Analog ground connection. Return for the internal voltage reference and analog circuits.
BST	20	P/I	High-side driver supply for bootstrap gate drive. Connect to the cathode of the external bootstrap diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side N-channel MOSFET gate and should be placed as close to controller as possible. An internal BST charge pump will supply 200 µA current into bootstrap capacitor for bypass operation.
COMP	11	O	Output of the internal error amplifier. The loop compensation network should be connected between this pin and the FB pin.
CSN	3	I	Inverting input of current sense amplifier. Connect to the negative-side of the current sense resistor.
CSP	4	I	Non-inverting input of current sense amplifier. Connect to the positive-side of the current sense resistor.
DG	2	O	Disconnection switch control pin. Connect to the gate terminal of the N-channel MOSFET disconnection switch.
DS	1	I/O	Source connection of N-channel MOSFET disconnection switch. Connect to the source terminal of the disconnection switch, the cathode terminal of the freewheeling diode and the supply input of boost inductor.
EP	EP	N/A	Exposed pad of the package. No internal electrical connections. Should be soldered to the large ground plane to reduce thermal resistance.
FB	10	I	Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets the output voltage level. The regulation threshold at the FB pin is 1.2 V.
HO	19	O	High-side N-channel MOSFET gate drive output. Connect to the gate of the high-side synchronous N-channel MOSFET switch through a short, low inductance path.
LO	16	O	Low-side N-channel MOSFET gate drive output. Connect to the gate of the low-side N-channel MOSFET switch through a short, low inductance path.
MODE	13	I	Switching mode selection pin. Internal 700 kΩ pull-up and 100 kΩ pull-down resistor hold MODE pin to 0.15 V as a default. By adding external pull-up or pull-down resistor, MODE pin voltage can be programmed. When MODE pin voltage is greater than 1.2 V, diode emulation mode threshold, forced PWM mode is enabled, allowing current to flow in either direction through the high-side N-channel MOSFET switch. When MODE pin voltage is less than 1.2 V, the controller works in diode emulation mode. Skip cycle comparator is activated as a default condition when the MODE pin is left floating. If the MODE pin is grounded, the controller still operates in diode emulation mode, but the skip cycle comparator will not be triggered in normal operation, this enables pulse skipping operation at light load.
PGND	15	G	Power ground connection pin for low-side N-channel MOSFET gate driver. Connect directly to the source terminal of the low-side N-channel MOSFET switch.
RES	14	O	The restart timer pin for an external capacitor that configures hiccup mode off-time and restart delay during over load conditions and hiccup mode short circuit protection. Connect directly to the AGND when hiccup mode operation is not required.
SLOPE	12	I	Slope compensation is programmed by an external resistor between SLOPE and the AGND.
SS	7	I	Soft-start programming pin. An external capacitor and an internal 10 μA current source set the ramp rate of the internal error amplifier reference during soft-start.
SW	18	I/O	Switching node of the boost regulator. Connect to the bootstrap capacitor, the source terminal of the high-side N-channel MOSFET switch and the drain terminal of the low-side N-channel MOSFET switch through short, low inductance paths.
SYNCIN/RT	8	I	The internal oscillator frequency is programmed by an external resistor between RT and the AGND. The internal oscillator can be synchronized to an external clock by applying a positive pulse signal into this pin. The recommended maximum internal oscillator frequency is 2 MHz which leads to 1 MHz maximum switching frequency.
UVLO	6	I	Undervoltage lockout programming pin. If the UVLO pin is below 0.4 V, the regulator is in the shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V, the regulator is in standby mode with the VCC regulator operational and no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.2 V, the startup sequence begins. A 10 μA current source at UVLO pin is enabled when UVLO exceeds 1.2 V and flows through the external UVLO resistors to provide hysteresis. The UVLO pin should not be left floating.
VCC	17	P/O/I	VCC bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller as possible.
VIN	5	P/I	Supply voltage input source for the VCC regulator. Connect to the input capacitor and source power supply connection with short, low impedance paths.

(1) G = Ground, I = Input, O = Output, P = Power

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input	VIN, CSP, CSN	–0.3	75	V
	BST to SW, FB, MODE, UVLO, VCC⁽²⁾	–0.3	15
	SW	–5.0	105
	BST	–0.3	115
	SS, SLOPE, SYNCIN/RT	–0.3	7
	CSP to CSN, PGND	–0.3	0.3
Output⁽³⁾	DG to DS	–3.0	18
	DG to VIN	–75	15
	DS	–3.0	75
	HO to SW	–0.3	BST to SW+0.3
	LO	–0.3	VCC+0.3
	COMP, RES	–0.3	7
Thermal	Junction Temperature	–40	150	ºC
T_stg	Storage temperature range	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless otherwise specified, all voltages are referenced to AGND pin.

(2) See Application Information when input supply voltage is less than the VCC voltage.

(3) All output pins are not specified to have an external voltage applied.

6.2 ESD Ratings: LM5121

			VALUE	UNIT

V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2	kV
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDED specification JESD22-C101 ⁽²⁾	±1	kV

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings: LM5121-Q1

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±2	kV
		Charged device model (CDM), per AEC Q100-011	Corner pins	±1
		Charged device model (CDM), per AEC Q100-011	Other pins	±1

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.4 Recommended Operating Conditions⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Input supply voltage⁽²⁾	VIN	4.5	65	V
Disconnection switch voltage⁽²⁾	DG, DS	3.0	65
Low-side driver bias voltage	VCC		14
High-side driver bias voltage	BST to SW	3.8	14
Current sense common mode range⁽²⁾	CSP, CSN	3.0	65
Switch node voltage	SW		100
Junction temperature	T_J	–40	125	ºC

(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional, but does not guarantee specific performance limits.

(2) Minimum VIN operating voltage is always 4.5 V. The minimum input power supply voltage can be 3.0 V after start-up, assuming VIN voltage is supplied from an available external source.

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		LM5121, LM5121-Q1	UNIT
		PWP (HTSSOP)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance (Typ.)	40	ºC/W
R_θJC(bot)	Junction-to-case (bot) thermal resistance (Typ.)	4	ºC/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

Unless otherwise specified, these specifications apply for –40°C ≤ T_J ≤ +125°C, V_VIN = 12 V, V_VCC = 8.3 V, R_T = 20 kΩ, no load on LO and HO. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only.

		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VIN SUPPLY
I_SHUTDOWN	VIN shutdown current	V_UVLO = 0 V		9	17	µA
I_BIAS	VIN operating current (exclude the current into RT resistor)	V_UVLO = 2 V, non-switching		4	5	mA
VCC REGULATOR
V_CC(REG)	VCC regulation	No load	6.9	7.6	8.3	V
	VCC dropout (VIN to VCC)	V_VIN = 4.5 V, no external load			0.25
	VCC dropout (VIN to VCC)	V_VIN = 4.5 V, I_VCC = 25 mA		0.28	0.5
	VCC sourcing current limit	V_VCC = 0 V	50	62		mA
I_VCC	VCC operating current (exclude the current into RT resistor)	V_VCC = 8.3 V		3.5	5
I_VCC		V_VCC = 12 V		4.5	8
	VCC undervoltage threshold	VCC rising, V_VIN = 4.5 V	3.9	4.0	4.1	V
	VCC undervoltage threshold	VCC falling, V_VIN = 4.5 V			3.7
	VCC undervoltage hysteresis			0.385
UNDERVOLTAGE LOCKOUT
	UVLO threshold	UVLO rising	1.17	1.20	1.23	V
	UVLO hysteresis current	V_UVLO = 1.4 V	7	10	13	µA
	UVLO standby threshold	UVLO rising	0.3	0.4	0.5	V
	UVLO standby hysteresis			0.1	0.125	V
MODE
	Diode emulation mode threshold	MODE rising	1.20	1.24	1.28	V
	Diode emulation mode hysteresis			0.1		V
	Default MODE voltage		145	155	170	mV
	Default skip cycle threshold	COMP rising, measured at COMP		1.290		V
	Default skip cycle threshold	COMP falling, measured at COMP		1.245		V
	Skip cycle hysteresis	Measured at COMP		40		mV
ERROR AMPLIFIER
V_REF	FB reference voltage	Measured at FB, V_FB= V_COMP	1.188	1.200	1.212	V
	FB input bias current	V_FB= V_REF		5		nA
V_OH	COMP output high voltage	I_SOURCE = 2 mA, V_VCC = 4.5 V	2.75			V
V_OH	COMP output high voltage	I_SOURCE = 2 mA, V_VCC = 12 V	3.40
V_OL	COMP output low voltage	I_SINK = 2 mA			0.25
A_OL	DC gain			80		dB
f_BW	Unity gain bandwidth			3		MHz
OSCILLATOR
f_SW1	Switching frequency 1	R_T = 20 kΩ	400	450	500	kHz
f_SW2	Switching frequency 2	R_T = 10 kΩ	775	875	975	kHz
	RT output voltage			1.2		V
	RT sync rising threshold	RT rising		2.5	2.9
	RT sync falling threshold	RT falling	1.6	2.0
	Minimum sync pulse width		100			ns
DISCONNECTION SWITCH CONTROL
I_DIS-SOURCE	DG current source	UVLO = 2 V, Sourcing		25		uA
I_DIS-SINK	DG current sink	Inrush Control, Sinking		67		uA
	DG discharge switch R_DS-ON	Circuit Breaker		38		Ω
	DG charge pump regulation	DG to VIN, No load, V_VIN = 4.5 V	9.5	10.5	11.5	V
	DG charge pump regulation	DG to VIN, No load, V_VIN = 12 V			12.5
V_GS-DET	V_GS detection threshold	DG to DS, Rising, V_VIN = 12 V	4.0	5.4	6.5
	V_GS detection hysteresis			0.2
	Transconductance gain	CSP to CSN to I_DG		12		uA/mV
SLOPE COMPENSATION
	SLOPE output voltage		1.17	1.20	1.23	V
V_SLOPE	Slope compensation amplitude	R_SLOPE = 20 kΩ, f_SW = 100 kHz, 50% duty cycle, T_J = –40ºC to +125ºC	1.375	1.650	1.925
V_SLOPE	Slope compensation amplitude	R_SLOPE= 20 kΩ, f_SW= 100 kHz, 50% duty cycle, T_J = 25ºC	1.400	1.650	1.900
SOFT-START
I_SS-SOURCE	SS current source	V_SS = 0 V	7.5	10	12	µA
	SS discharge switch R_DS-ON			13		Ω
PWM COMPARATOR
t_LO-OFF	Forced LO off-time	V_VCC = 5.5 V		420	550	ns
t_LO-OFF	Forced LO off-time	V_VCC = 4.5 V		360	500
t_ON-MIN	Minimum LO on-time	R_SLOPE = 20 kΩ		150
t_ON-MIN	Minimum LO on-time	R_SLOPE = 200 kΩ		300
	COMP to PWM voltage drop	T_J = –40ºC to +125ºC	0.95	1.10	1.25	V
	COMP to PWM voltage drop	T_J = 25ºC	1.00	1.10	1.20	V
CURRENT SENSE / CYCLE-BY-CYCLE CURRENT LIMIT
V_CS-TH1	Cycle-by-cycle current limit threshold	CSP to CSN, T_J = –40ºC to +125ºC	65.5	75.0	87.5	mV
V_CS-TH1	Cycle-by-cycle current limit threshold	CSP to CSN, T_J = 25ºC	67.0	75.0	86.0
		V_CS-TH2 –V_CS-TH1	5
V_CS-TH2	Inrush current limit threshold	CSP to CSN	80	110	133
V_CS-TH3	Circuit breaker enable threshold	CSP to CSN, Rising	143	160	170
		V_CS-TH3 – V_CS-TH2	20
V_CS-TH4	Circuit breaker disable threshold	CSP to CSN, Falling	4.0	11.5	16.0
V_CS-ZCD	Zero cross detection threshold	CSP to CSN, Rising		7
V_CS-ZCD	Zero cross detection threshold	CSP to CSN, Falling	0.3	6	12
	Current sense amplifier gain			10		V/V
I_CSP	CSP input bias current			12		µA
I_CSN	CSN input bias current			11
	Bias current matching	I_CSP to I_CSN	–1.75	1	3.75
	CS to LO delay	Current sense / current limit delay		150		ns
HICCUP MODE RESTART
V_RES	Restart threshold	RES rising	1.15	1.20	1.25	V
V_HCP-UPPER	Hiccup counter upper threshold	RES rising		4.2
V_HCP-UPPER	Hiccup counter upper threshold	RES rising, V_VIN = V_VCC = 4.5 V		3.6
V_HCP-LOWER	Hiccup counter lower threshold	RES falling		2.15
V_HCP-LOWER	Hiccup counter lower threshold	RES falling, V_VIN = V_VCC = 4.5 V		1.85
I_RES-SOURCE1	RES current source1	Fault-state charging current	20	30	40	µA
I_RES-SINK1	RES current sink1	Normal-state discharging current		5
I_RES-SOURCE2	RES current source2	Hiccup mode off-time charging current		10
I_RES-SINK2	RES current sink2	Hiccup mode off-time discharging current		5
	Hiccup cycle			8		Cycles
	RES discharge switch R_DS-ON			40		Ω
	Ratio of hiccup mode off-time to restart delay time			122
HO GATE DRIVER
V_OHH	HO high-state voltage drop	I_HO = –100 mA, V_OHH = V_BST – V_HO		0.15	0.24	V
V_OLH	HO low-state voltage drop	I_HO = 100 mA, V_OLH = V_HO – V_SW		0.1	0.18	V
	HO rise time (10% to 90%)	C_LOAD = 4700 pF, V_BST = 12 V		25		ns
	HO fall time (90% to 10%)	C_LOAD = 4700 pF, V_BST = 12 V		20		ns
I_OHH	Peak HO source current	V_HO = 0 V, V_SW = 0 V, V_BST = 4.5 V		0.8		A
I_OHH	Peak HO source current	V_HO = 0 V, V_SW = 0 V, V_BST = 7.6 V		1.9
I_OLH	Peak HO sink current	V_HO = V_BST = 4.5 V		1.9
I_OLH	Peak HO sink current	V_HO = V_BST = 7.6 V		3.2
I_BST	BST charge pump sourcing current	V_VIN = V_SW = 9.0 V , V_BST - V_SW = 5.0 V	90	200		µA
	BST charge pump regulation	BST to SW, I_BST= –70 μA, V_VIN = V_SW = 9.0 V	5.3	6.2	6.75	V
	BST charge pump regulation	BST to SW, I_BST = –70 μA, V_VIN = V_SW = 12 V	7	8.5	9
	BST to SW undervoltage		2.0	3.0	3.5
	BST DC bias current	V_BST - V_SW = 12 V, V_SW = 0 V		30	45	µA
LO GATE DRIVER
V_OHL	LO high-state voltage drop	I_LO = –100 mA, V_OHL = V_VCC – V_LO		0.15	0.25	V
V_OLL	LO low-state voltage drop	I_LO = 100 mA, V_OLL = V_LO		0.1	0.17	V
	LO rise time (10% to 90%)	C_LOAD = 4700 pF		25		ns
	LO fall time (90% to 10%)	C_LOAD = 4700 pF		20		ns
I_OHL	Peak LO source current	V_LO= 0 V, V_VCC = 4.5 V		0.8		A
I_OHL	Peak LO source current	V_LO = 0 V		2.0
I_OLL	Peak LO sink current	V_LO = V_VCC = 4.5 V		1.8
I_OLL	Peak LO sink current	V_LO = V_VCC		3.2
SWITCHING CHARACTERISTICS
t_DLH	LO fall to HO rise delay	No load, 50% to 50%	50	80	115	ns
t_DHL	HO fall to LO rise delay	No load, 50% to 50%	60	80	105	ns
THERMAL
T_SD	Thermal shutdown	Temperature rising		165		ºC
	Thermal shutdown hysteresis			25		ºC