JAJSFD4A May   2018  – November 2018 LM5122ZA

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Undervoltage Lockout (UVLO)
      2. 8.3.2  High-Voltage VCC Regulator
      3. 8.3.3  Oscillator
      4. 8.3.4  Slope Compensation
      5. 8.3.5  Error Amplifier
      6. 8.3.6  PWM Comparator
      7. 8.3.7  Soft Start
      8. 8.3.8  HO and LO Drivers
      9. 8.3.9  Bypass Operation (VOUT = VIN)
      10. 8.3.10 Cycle-by-Cycle Current Limit
      11. 8.3.11 Clock Synchronization
      12. 8.3.12 Maximum Duty Cycle
      13. 8.3.13 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Control (Forced-PWM Mode and Diode-Emulation Mode)
      2. 8.4.2 MODE Control (Skip-Cycle Mode and Pulse-Skipping Mode)
      3. 8.4.3 Hiccup-Mode Overload Protection
      4. 8.4.4 Slave Mode and SYNCOUT
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Feedback Compensation
      2. 9.1.2 Sub-Harmonic Oscillation
      3. 9.1.3 Interleaved Boost Configuration
      4. 9.1.4 DCR Sensing
      5. 9.1.5 Output Overvoltage Protection
      6. 9.1.6 SEPIC Converter Simplified Schematic
      7. 9.1.7 Non-Isolated Synchronous Flyback Converter Simplified Schematic
      8. 9.1.8 Negative to Positive Conversion
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Timing Resistor RT
        2. 9.2.2.2  UVLO Divider RUV2, RUV1
        3. 9.2.2.3  Input Inductor LIN
        4. 9.2.2.4  Current Sense Resistor RS
        5. 9.2.2.5  Current Sense Filter RCSFP, RCSFN, CCS
        6. 9.2.2.6  Slope Compensation Resistor RSLOPE
        7. 9.2.2.7  Output Capacitor COUT
        8. 9.2.2.8  Input Capacitor CIN
        9. 9.2.2.9  VIN Filter RVIN, CVIN
        10. 9.2.2.10 Bootstrap Capacitor CBST and Boost Diode DBST
        11. 9.2.2.11 VCC Capacitor CVCC
        12. 9.2.2.12 Output Voltage Divider RFB1, RFB2
        13. 9.2.2.13 Soft-Start Capacitor CSS
        14. 9.2.2.14 Restart Capacitor CRES
        15. 9.2.2.15 Low-Side Power Switch QL
        16. 9.2.2.16 High-Side Power Switch QH and Additional Parallel Schottky Diode
        17. 9.2.2.17 Snubber Components
        18. 9.2.2.18 Loop Compensation Components CCOMP, RCOMP, CHF
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.8 HO and LO Drivers

The LM5122ZA contains strong N-channel MOSFET gate drivers and an associated high-side level shifter to drive the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external boot diode DBST, and bootstrap capacitor CBST. During the on-time of the low-side N-channel MOSFET driver, the SW pin voltage is approximately 0 V, and the CBST is charged from VCC through the DBST. TI recommends a 0.1-μF or larger ceramic capacitor, connected with short traces between the BST and SW pin.

The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO fall to LO rise delay). Similarly, the HO turnon is delayed until the LO voltage has discharged. HO is then enabled after a small delay (LO fall to HO rise delay). This technique insures adequate dead-time for any size N-channel MOSFET device, especially when VCC is supplied by a higher external voltage source. Be careful when adding series gate resistors, as this may decrease the effective dead time.

Exercise care when selecting the N-channel MOSFET devices threshold voltage, especially if the VIN voltage range is below the VCC regulation level or a bypass operation is required. If the bypass operation is required, especially when output voltage is less than 12 V, select a logic level device for the high-side N-channel MOSFET. During start-up at low input voltages, the low-side N-channel MOSFET switch gate plateau voltage must be sufficient to completely enhance the N-channel MOSFET device. If the low-side N-channel MOSFET drive voltage is lower than the low-side N-channel MOSFET device gate plateau voltage during startup, the regulator may not start up properly and it may stick at the maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower threshold N-channel MOSFET switch or by increasing VIN(STARTUP) with the UVLO pin voltage programming.