JAJSKQ9 データシート

JAJSKQ9B December 2021 – December 2022 LM5123-Q1

PRODUCTION DATA

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

RGR|20

サーマルパッド・メカニカル・データ

発注情報

8.3.5 Line Undervoltage Lockout (UVLO Pin)

When UVLO is greater than the UVLO threshold (V_UVLO), the device enters active mode if the device configuration is finished. UVLO hysteresis is accomplished with an internal 25-mV voltage hysteresis (V_UVLO-HYS) at the UVLO pin, and an additional 10-μA current sink (I_UVLO-HYS) that is switched on or off. When the UVLO pin voltage exceeds V_UVLO, the current sink is disabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below V_UVLO or during the device configuration time, the current sink is enabled, causing the voltage at the UVLO pin to fall quickly.

The external UVLO resistor voltage divider (R_UVLOT, R_UVLOB) must be designed so that the voltage at the UVLO pin is greater than V_UVLO when V_SUPPLY is in the desired operating range. The values of R_UVLOT and R_UVLOB can be calculated as follows.

Equation 2.

R_{U V L O T} = \frac{(V_{S U P P L Y_O N} - \frac{V_{U V L O_R I S I N G}}{V_{U V L O_F A L L I N G}} \times V_{S U P P L Y_O F F})}{I_{U V L O_H Y S}}

Equation 3.

R_{U V L O B} = \frac{V_{U V L O_F A L L I N G} \times R_{U V L O T}}{V_{S U P P L Y_O F F} - V_{U V L O_F A L L I N G}}

A UVLO capacitor (C_UVLO) is required in case V_SUPPLY drops below V_SUPPLY-OFF momentarily during the start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an additional series UVLO resistor (R_UVLOS) can be used to quickly raise the voltage at the UVLO pin when I_UVLO-HYS is disabled.

The UVLO pin can be connected to the BIAS pin if not used. Drive the UVLO pin through a minimum of a 5-kΩ resistor if the BIAS pin voltage is less than the UVLO pin voltage in any conditions.