JAJSKQ9B December   2021  – December 2022 LM5123-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Enable/Disable (EN, VH Pin)
      2. 8.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 8.3.3  Light Load Switching Mode Selection (MODE Pin)
      4. 8.3.4  VOUT Range Selection (RANGE Pin)
      5. 8.3.5  Line Undervoltage Lockout (UVLO Pin)
      6. 8.3.6  Fast Restart using VCC HOLD (VH Pin)
      7. 8.3.7  Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)
      8. 8.3.8  Overvoltage Protection (VOUT Pin)
      9. 8.3.9  Power Good Indicator (PGOOD Pin)
      10. 8.3.10 Dynamically Programmable Switching Frequency (RT)
      11. 8.3.11 External Clock Synchronization (SYNC Pin)
      12. 8.3.12 Programmable Spread Spectrum (DITHER Pin)
      13. 8.3.13 Programmable Soft Start (SS Pin)
      14. 8.3.14 Wide Bandwidth Transconductance Error Amplifier and PWM (TRK, COMP Pin)
      15. 8.3.15 Current Sensing and Slope Compensation (CSP, CSN Pin)
      16. 8.3.16 Constant Peak Current Limit (CSP, CSN Pin)
      17. 8.3.17 Maximum Duty Cycle and Minimum Controllable On-Time Limits
      18. 8.3.18 Deep Sleep Mode and Bypass Operation (HO, CP Pin)
      19. 8.3.19 MOSFET Drivers, Integrated Boot Diode, and Hiccup Mode Fault Protection (LO, HO, HB Pin)
      20. 8.3.20 Thermal Shutdown Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Status
        1. 8.4.1.1 Shutdown Mode
        2. 8.4.1.2 Configuration Mode
        3. 8.4.1.3 Active Mode
        4. 8.4.1.4 Sleep Mode
        5. 8.4.1.5 Deep Sleep Mode
      2. 8.4.2 Light Load Switching Mode
        1. 8.4.2.1 Forced PWM (FPWM) Mode
        2. 8.4.2.2 Diode Emulation (DE) Mode
        3. 8.4.2.3 Forced Diode Emulation Operation in FPWM Mode
        4. 8.4.2.4 Skip Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Ideas
      3. 9.2.3 Application Curves
    3. 9.3 System Example
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGR|20
サーマルパッド・メカニカル・データ
発注情報

8.3.7 Adjustable Output Regulation Target (VOUT, TRK, VREF Pin)

The VOUT regulation target (VOUT-REG) is adjustable by programming the TRK pin voltage, which is the reference of the internal error amplifier. The accuracy of VOUT-REG is given when the TRK voltage is between 0.25 V and 1.0 V. The high impedance TRK pin allows users to program the pin voltage directly by a D/A converter or by connecting to a resistor voltage divider (RVREFT, RVREFB) between VREF and AGND.

The device provides a 1-V voltage reference (VREF), which can be used to program the TRK pin voltage through a resistor voltage divider. It is not recommended to use VREF as a reference voltage of an external circuit because the device periodically disables VREF in sleep or deep sleep mode. For stability reasons, the VREF capacitor (CVREF) should be between 330 pF and 1 nF. 470 pF is recommended.

When RVREFT and RVREFB are used to program the TRK pin voltage, VOUT-REG can be calculated as follows.

Lower VOUT Range
Equation 4. V O U T _ R E G = 20 × R V R E F B R V R E F B + R V R E F T
Upper VOUT Range
Equation 5. V O U T _ R E G = 60 × R V R E F B R V R E F B + R V R E F T

The TRK pin voltage can be dynamically programmed in active mode, which makes an envelope tracking power supply design easy. When designing a tracking power supply, it is required to adjust the TRK pin voltage slow enough so that the VOUT pin voltage can track the command and the internal overvoltage or undervoltage comparator is not triggered during the transient operation. An RC filter must be used at the TRK pin to slow down the slew rate of the command signal at the TRK pin, especially when a step input is applied. When a trapezoidal or sinusoidal input is applied, the slew rate or the frequency of the command signal must be limited.

GUID-20200809-CA0I-PSWK-CSVF-6PTHCHZMKKPH-low.gif Figure 8-6 TRK Control (a) using VREF (b) by External Step Input

In FPWM operation, VOUT-REG tracks the TRK pin voltage immediately as well during deep sleep mode. While in skip or diode mode operation, VOUT-REG tracks the TRK pin voltage pin voltage with a maximum of a 20 ms delay during deep sleep mode to save power. Take extra care when programming TRK if VSUPPLY is greater than VOUT-REG in any conditions. The device enters active mode with a 5-μs delay if VLOAD falls down below VOUT-REG in deep sleep mode, but the device enters active mode with maximum of a 20 ms delay if VOUT-REG is increased by TRK above VLOAD in deep sleep mode.