JAJSV63A August   2024  – August 2024 LM5137-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
      3. 7.3.3  Precision Enable (EN1, EN2)
      4. 7.3.4  Switching Frequency (RT)
      5. 7.3.5  Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      6. 7.3.6  Synchronization Out (SYNCOUT)
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Configurable Soft Start (RSS)
      9. 7.3.9  Output Voltage Setpoints (FB1, FB2)
      10. 7.3.10 Minimum Controllable On-Time
      11. 7.3.11 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
        1. 7.3.11.1 Slope Compensation
      12. 7.3.12 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
        1. 7.3.12.1 Shunt Current Sensing
        2. 7.3.12.2 Inductor DCR Current Sensing
      13. 7.3.13 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
      14. 7.3.14 Output Configurations (CNFG)
        1. 7.3.14.1 Independent Dual-Output Operation
        2. 7.3.14.2 Single-Output Interleaved Operation
        3. 7.3.14.3 Single-Output Multiphase Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
      2. 7.4.2 PFM Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Power MOSFETs
        2. 8.1.1.2 Buck Inductor
        3. 8.1.1.3 Output Capacitors
        4. 8.1.1.4 Input Capacitors
        5. 8.1.1.5 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V Automotive Battery Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3 Inductor Calculations
          4. 8.2.1.2.4 Shunt Resistors
          5. 8.2.1.2.5 Ceramic Output Capacitors
          6. 8.2.1.2.6 Ceramic Input Capacitors
          7. 8.2.1.2.7 Feedback Resistors
          8. 8.2.1.2.8 Input Voltage UVLO Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Automotive Applications
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Stage Layout
        2. 8.4.1.2 Gate Drive Layout
        3. 8.4.1.3 PWM Controller Layout
        4. 8.4.1.4 Thermal Design and Layout
        5. 8.4.1.5 Ground Plane Design
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Connect the exposed pad on the bottom to AGND and PGND on the PCB.
Figure 5-1 RHA Package, 36-pin VQFN With Wettable Flanks (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
FB2 1 I Connect FB2 through a 7.5kΩ, 24.9kΩ or 48.7kΩ resistor to VDDA to set the output voltage at 3.3V, 5V or 12V, respectively. Alternatively, use a resistive divider from VOUT2 to FB2 to set the output voltage setpoint of channel 2 between 0.8V and 60V. The FB2 regulation voltage is 0.8V.
VOUT2 3 I Output voltage sense and the current sense amplifier input of channel 2. Connect VOUT2 to the output side of the channel 2 current sense resistor (or to the relative sense capacitor terminal if inductor DCR current sensing is used).
ISNS2+ 4 I Channel 2 current sense amplifier input. Connect ISNS2+ to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
PG2 5 O An open-collector output that goes low if VOUT2 is outside a specific regulation window
EN2 6 I An active high input (VEN2 > 1V typical) enables channel 2. If VEN2 < 0.5V, channel 2 is disabled and is in shutdown mode unless a SYNC signal is present at PFM/SYNC pin. EN2 must never be left floating.
VIN 8 P Supply voltage input source for the VCC regulator
HO2 9 P Channel 2 high-side gate driver output
SW2 10 P Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
CBOOT2 11 P Channel 2 high-side driver supply for bootstrap gate drive
LO2 12 P Channel 2 low-side gate driver output
PGND 13 G Power ground connection pin for the low-side MOSFET gate driver
VCC 14 P VCC bias supply pin. Connect a ceramic capacitor between VCC and PGND.
LO1 15 P Channel 1 low-side gate driver output
CBOOT1 16 P Channel 1 high-side driver supply for bootstrap gate drive
SW1 17 P Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET, and the drain terminal of the low-side MOSFET.
HO1 18 P Channel 1 high-side gate driver output
EN1 20 O An active high input (VEN1 > 1V) enables channel 1. If VEN1 < 0.5V, channel 1 is disabled and is in shutdown mode unless a SYNC signal is present at PFC/SYNC pin. EN1 must never be left floating.
PG1 21 O An open-collector output that goes low if VOUT1 is outside a specified regulation window.
ISNS1+ 22 I Channel 1 current sense amplifier input. Connect ISNS1+ to the inductor side of the external current sense resistor (or to the relevant sense capacitor terminal if inductor DCR current sensing is used) using a low-current Kelvin connection.
BIAS1/VOUT1 23 I If VBIAS1 > 4.3V, BIAS1 becomes the supply voltage to the internal VCC regulator. BIAS1 also acts as the primary VOUT1 sensing for fixed VOUT options.
CNFG 26 I Connect a resistor from CNFG to GND to set the output configuration and to activate DRSS at one of two modulation frequencies (or to disable). Refer to Table 7-3.
FB1 25 I Connect FB1 through a 7.5kΩ, 24.9kΩ or 48.7kΩ resistor to VDDA to set the output voltage at 3.3V, 5V or 12V, respectively. Alternatively, use a resistive divider from VOUT1 to FB1 to set the output voltage setpoint of channel 1 between 0.8V and 60V. The FB1 regulation voltage is 0.8V.
COMP1 28 O Output of the channel 1 transconductance error amplifier. COMP1 is high impedance in interleaved or secondary mode. Pulling COMP1 below 100mV in interleaved mode disables the HO1 and LO1 gate driver outputs.
RSS 29 O Connect a resistor from RSS to GND to set the soft-start time between 1.5ms and 20ms
RT 30 O Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz.
AGND 31 G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
VDDA 32 P Internal analog bias regulator output. Connect a 1µF ceramic decoupling capacitor from VDDA to AGND.
SYNCOUT 33 O SYNCOUT is a logic-level signal with a rising edge approximately 90° lagging HO1 (or 90° leading HO2). When SYNCOUT is used to synchronize a second LM5137-Q1 controller, the phases operate at 0°, 90°, 180° and 270° as needed.
PFM/SYNC 34 I Connect PFM/SYNC to VDDA to operate the LM5137-Q1 in PFM mode. Connect PFM/SYNC to GND to enable forced PWM (FPWM) mode with continuous conduction at light loads. Use PFM/SYNC as a synchronization input to synchronize the internal oscillator to an external clock.
COMP2 35 O Output of the channel 2 transconductance error amplifier. COMP2 is high impedance in single-output interleaved mode. Pulling COMP2 below 100mV in interleaved mode disables the HO2 and LO2 gate driver outputs.
GND 2, 7, 19, 24, 27, 36 G Unused pins – connect to the exposed pad on the PCB.
(1) P = Power, G = Ground, I = Input, O = Output