JAJSV63A August   2024  – August 2024 LM5137-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
      3. 7.3.3  Precision Enable (EN1, EN2)
      4. 7.3.4  Switching Frequency (RT)
      5. 7.3.5  Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      6. 7.3.6  Synchronization Out (SYNCOUT)
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Configurable Soft Start (RSS)
      9. 7.3.9  Output Voltage Setpoints (FB1, FB2)
      10. 7.3.10 Minimum Controllable On-Time
      11. 7.3.11 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
        1. 7.3.11.1 Slope Compensation
      12. 7.3.12 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
        1. 7.3.12.1 Shunt Current Sensing
        2. 7.3.12.2 Inductor DCR Current Sensing
      13. 7.3.13 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
      14. 7.3.14 Output Configurations (CNFG)
        1. 7.3.14.1 Independent Dual-Output Operation
        2. 7.3.14.2 Single-Output Interleaved Operation
        3. 7.3.14.3 Single-Output Multiphase Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
      2. 7.4.2 PFM Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Power MOSFETs
        2. 8.1.1.2 Buck Inductor
        3. 8.1.1.3 Output Capacitors
        4. 8.1.1.4 Input Capacitors
        5. 8.1.1.5 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V Automotive Battery Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3 Inductor Calculations
          4. 8.2.1.2.4 Shunt Resistors
          5. 8.2.1.2.5 Ceramic Output Capacitors
          6. 8.2.1.2.6 Ceramic Input Capacitors
          7. 8.2.1.2.7 Feedback Resistors
          8. 8.2.1.2.8 Input Voltage UVLO Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Automotive Applications
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Stage Layout
        2. 8.4.1.2 Gate Drive Layout
        3. 8.4.1.3 PWM Controller Layout
        4. 8.4.1.4 Thermal Design and Layout
        5. 8.4.1.5 Ground Plane Design
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.3.1 Design Requirements

Table 8-6 shows the intended input, output, and performance parameters for this circuit example.

Table 8-6 Design Parameters
DESIGN PARAMETERVALUE
Input voltage range (steady state)36V to 65V
Minimum transient input voltage30V
Maximum transient input voltage72V
Output voltage12V
Output current20A
Switching frequency400kHz
Target efficiency at 20A 95.5%
Input voltage UVLO on, off34V, 28V
No-load sleep current with phase 2 disabled< 20µA
Shutdown current4µA

Resistor RRT of 57.6kΩ sets the switching frequency at 400kHz. In terms of control loop performance, the target loop crossover frequency is 60kHz with a phase margin greater than 50°. An RSS resistance of 20kΩ sets the output voltage soft-start time to 4.6ms.

Table 8-7 cites the selected buck regulator powertrain components, with many of the components available from multiple vendors. This design uses 80V logic-level MOSFETs, shielded buck inductors, shunt resistors with wide aspect ratio for low ESL, 100V-rated ceramic input capacitors and 25V-rated ceramic output capacitors.

Table 8-7 List of Materials for Application Circuit 3
REFERENCE DESIGNATORQTYSPECIFICATION(1)MANUFACTURERPART NUMBER
CIN1, CIN2 84.7µF, 100V, X7S, 1210, ceramic, AEC-Q200TDKCGA6M3X7S2A475K200
MurataGCM32DC72A475KE02L
COUT1, COUT2 8 22µF, 25V, X7R, 1210, ceramic, AEC-Q200TDKCGA6P3X7R1E226M250
22µF, 25V, X7S, 1210, ceramic, AEC-Q200MurataGCM32EC71E226KE36
LO1, LO224.7µH, 8.3mΩ, 15.7A, 10.85 × 10 × 5.2mm, AEC-Q200CyntecVCHA105D-4R7MS6
4.7µH, 9mΩ, 17A, 11 × 10 × 5.1mm, AEC-Q200 Bourns SRP1050WA-4R7M
4.7µH, 11.7mΩ, 13A, 10.8 × 10 × 5mm, AEC-Q200EatonHCM1A1105V2-4R7-R
4.7µH, 13.5mΩ, 16A, 10.85 × 10 × 3.8mm, AEC-Q200Würth Electronik784373680047
Q1, Q3280V, 13.4mΩ, 8nC, SON 5 × 6, AEC-Q101onsemiNVMFS6H852NLT1G
Q2, Q4 2 80V, 6.2mΩ, 16nC, SON 5 × 6, AEC-Q101 onsemi NVMFS6H836NLT1G
RS1, RS22Shunt, 4mΩ ±1%, ±50ppm/°C, 0612, 1.5W, AEC-Q200SusumuKRL3216E-C-R004-F
U11LM5137-Q1 80V two-phase buck controller, AEC-Q100Texas InstrumentsLM5137QRHARQ1
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