JAJSV63A August   2024  – August 2024 LM5137-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
      3. 7.3.3  Precision Enable (EN1, EN2)
      4. 7.3.4  Switching Frequency (RT)
      5. 7.3.5  Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      6. 7.3.6  Synchronization Out (SYNCOUT)
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Configurable Soft Start (RSS)
      9. 7.3.9  Output Voltage Setpoints (FB1, FB2)
      10. 7.3.10 Minimum Controllable On-Time
      11. 7.3.11 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
        1. 7.3.11.1 Slope Compensation
      12. 7.3.12 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
        1. 7.3.12.1 Shunt Current Sensing
        2. 7.3.12.2 Inductor DCR Current Sensing
      13. 7.3.13 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
      14. 7.3.14 Output Configurations (CNFG)
        1. 7.3.14.1 Independent Dual-Output Operation
        2. 7.3.14.2 Single-Output Interleaved Operation
        3. 7.3.14.3 Single-Output Multiphase Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
      2. 7.4.2 PFM Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Power MOSFETs
        2. 8.1.1.2 Buck Inductor
        3. 8.1.1.3 Output Capacitors
        4. 8.1.1.4 Input Capacitors
        5. 8.1.1.5 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V Automotive Battery Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3 Inductor Calculations
          4. 8.2.1.2.4 Shunt Resistors
          5. 8.2.1.2.5 Ceramic Output Capacitors
          6. 8.2.1.2.6 Ceramic Input Capacitors
          7. 8.2.1.2.7 Feedback Resistors
          8. 8.2.1.2.8 Input Voltage UVLO Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Automotive Applications
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Stage Layout
        2. 8.4.1.2 Gate Drive Layout
        3. 8.4.1.3 PWM Controller Layout
        4. 8.4.1.4 Thermal Design and Layout
        5. 8.4.1.5 Ground Plane Design
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.14.2 Single-Output Interleaved Operation

Based on a resistor RCNFG connected from CNFG to AGND, configure the LM5137-Q1 as for single-output interleaved operation. As shown in Table 7-6, use 41.2kΩ to disable DRSS and 54.9kΩ or 71.5kΩ to enable DRSS at 5% or 10% frequency spreading, respectively. This setup disables the error amplifier of channel 2 and places the error amplifier in a high impedance state. The controller is then in a primary, secondary configuration, and the SYNCOUT clock is 180° lagging HO2 (or 180° leading HO1).

As shown in Figure 7-8, connect COMP1 to COMP2 and use FB1 to set the output voltage setpoint.

Table 7-6 Configuration Modes for Single-Output Interleaved Operation
RCNFG PRIMARY / SECONDARY DRSS INDEPENDENT OR INTERLEAVED OUTPUTS
41.2kΩ Primary OFF Interleaved
54.9kΩ Primary DRSS1 Interleaved
71.5kΩ Primary DRSS2 Interleaved
LM5137-Q1 LM5137-Q1 Two-phase Regulator Schematic Configured for Single-output Interleaved Operation Figure 7-8 LM5137-Q1 Two-phase Regulator Schematic Configured for Single-output Interleaved Operation