JAJSV63A August 2024 – August 2024 LM5137-Q1
ADVANCE INFORMATION
The LM5137-Q1 contains an internal high-voltage VCC bias regulator that provides the bias supply for the PWM controller and the gate drivers of the external MOSFETs. Connect the input voltage pin (VIN) directly to an input voltage source up to 80V. When the input voltage is below the VCC setpoint of 5V, the VCC voltage tracks VIN minus a small voltage drop.
The VCC regulator current limit is 175mA (minimum). At power up, the regulator sources current into the VCC capacitor. When the VCC voltage exceeds 3.8V (typical), both output channels are enabled (if EN1 and EN2 are above 1V) and the soft-start sequence begins. Both channels remain active unless the VCC voltage falls below the falling UVLO threshold of 3.5V (typical) or EN is switched to a low state. Connect a 2.2µF to 10µF ceramic capacitor from VCC to PGND.
A 10Ω resistor connects VDDA to VCC. Bypass VDDA to AGND with a 1µF ceramic capacitor to achieve a low-noise internal bias rail. Normally VDDA is 5V, but there are two operating conditions where VDDA regulates at 3.3V. The first is in skip cycle mode when VOUT1 is set to 3.3V and VOUT2 is disabled. The second is in a cold-crank startup where VIN is 4V and VOUT1 is 3.3V.
If the BIAS1/VOUT1 voltage is above 4.3V, BIAS1/VOUT1 internally connects to a second input of the VCC regulator. This helps to reduce the internal power dissipation of the LM5137-Q1, as bias current derives from VOUT1 instead of VIN. Avoid connecting BIAS1/VOUT1 or VOUT2 to a voltage greater than 60V or less than –0.3V.
ITEM | OBSERVED BEHAVOR |
---|---|
1 | Upon recovering from sleep mode in PFM, with the oscillator frequency set above 1MHz and at load currents around 300mA, VCC is observed to loose regulation and can reach the falling UVLO threshold (3.5V). |