JAJSV63A August   2024  – August 2024 LM5137-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Wettable Flanks
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN)
      2. 7.3.2  Bias Supply Regulator (VCC, BIAS1/VOUT1, VDDA)
      3. 7.3.3  Precision Enable (EN1, EN2)
      4. 7.3.4  Switching Frequency (RT)
      5. 7.3.5  Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      6. 7.3.6  Synchronization Out (SYNCOUT)
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Configurable Soft Start (RSS)
      9. 7.3.9  Output Voltage Setpoints (FB1, FB2)
      10. 7.3.10 Minimum Controllable On-Time
      11. 7.3.11 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
        1. 7.3.11.1 Slope Compensation
      12. 7.3.12 Inductor Current Sense (ISNS1+, BIAS1/VOUT1, ISNS2+, VOUT2)
        1. 7.3.12.1 Shunt Current Sensing
        2. 7.3.12.2 Inductor DCR Current Sensing
      13. 7.3.13 MOSFET Gate Drivers (HO1, HO2, LO1, LO2)
      14. 7.3.14 Output Configurations (CNFG)
        1. 7.3.14.1 Independent Dual-Output Operation
        2. 7.3.14.2 Single-Output Interleaved Operation
        3. 7.3.14.3 Single-Output Multiphase Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode
      2. 7.4.2 PFM Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Power MOSFETs
        2. 8.1.1.2 Buck Inductor
        3. 8.1.1.3 Output Capacitors
        4. 8.1.1.4 Input Capacitors
        5. 8.1.1.5 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – Dual 5V and 3.3V, 20A Buck Regulator for 12V Automotive Battery Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 8.2.1.2.3 Inductor Calculations
          4. 8.2.1.2.4 Shunt Resistors
          5. 8.2.1.2.5 Ceramic Output Capacitors
          6. 8.2.1.2.6 Ceramic Input Capacitors
          7. 8.2.1.2.7 Feedback Resistors
          8. 8.2.1.2.8 Input Voltage UVLO Resistors
          9. 8.2.1.2.9 Compensation Components
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Design 3 – 12V, 20A, 400kHz, Two-Phase Buck Regulator for 48V Automotive Applications
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Power Stage Layout
        2. 8.4.1.2 Gate Drive Layout
        3. 8.4.1.3 PWM Controller Layout
        4. 8.4.1.4 Thermal Design and Layout
        5. 8.4.1.5 Ground Plane Design
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40°C to 150°C, Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN)
IQ-VIN1 VIN shutdown current Non-switching, VEN1 = VEN2 = 0V 4 µA
IQ-VIN2 VIN standby current Non-switching, 0.5V ≤ VEN1/2 ≤ 1V 130 µA
ISLEEP1 Sleep current, VVOUT1 = 5V, VVOUT2 = 3.3V
 		 1.05V ≤ VEN1/2 ≤ 80V, VVOUT1 = 5V,  VVOUT2 = 3.3V in regulation, no load, not switching 15.5 µA
ISLEEP2 Sleep current, VVOUT1 = 5V 1.05V ≤ VEN1 ≤ 80V, VEN2 = 0V, VVOUT1 = 5V in regulation, no load, not switching 12.7 24 µA
INTERNAL LDO (VCC)
VVCC-REG VCC regulation voltage IVCC = 0mA to 150mA 4.7 5.0 5.3 V
VVCC-OVP VCC OVP detect, VVCC rising 5.8 V
VVCC-OVP-HYS VCC OVP detect hysteresis 225 mV
VVCC-UVLO VCC UVLO rising threshold 3.8 V
VVCC-HYST VCC UVLO hysteresis  300 mV
IVCC-REG Internal LDO short-circuit current limit 175 225 mA
INTERNAL LDO (VDDA)
VVDDA-REG VDDA regulation voltage 5 V
RVDDA VDDA resistance to VCC 12 Ω
EXTERNAL BIAS (BIAS1)
VBIAS-ON VBIAS1/VOUT1 rising 4.1 4.3 4.4 V
VBIAS-HYST 130 mV
REFERENCE VOLTAGE (FB1, FB2)
VREF1 Regulated FB voltage 792 800 808 mV
VBG1 Bandgap1 voltage for regulation 1.2206 1.2237 1.2267 V
ENABLE (EN1, EN2)
VSDN1/2 Shutdown to standby threshold VEN1/2 rising 0.6 V
VEN1/2-HIGH Enable voltage rising threshold VEN1/2 rising, enable switching 0.95 1.0 1.05 V
IEN1/2-HYS Enable hystersis VEN1/2 = 1.1V –12 –10 –8 µA
OUTPUT VOLTAGE (VOUT1/BIAS1, VOUT2)
VOUT1/2-3.3V 3.3V output setpoint RFB1/2 = 7.5kΩ 3.267 3.3 3.33 V
VOUT1/2-5V
5V output setpoint
 		 RFB1/2 = 24.9kΩ 4.95 5.0 5.05 V
VOUT1/2-12V
12V output setpoint
 		 RFB1/2 = 48.7kΩ 11.88 12 12.12 V
ERROR AMPLIFIER (COMP1, COMP2)
gm1/2 EA transconductance ΔVFB  ±50mV 400 600 µS
VCOMP1/2-CLAMP COMP clamp voltage VFB1/2 = 0V 1.75 V
ICOMP1/2-SRC EA source current VCOMP1/2 = 1V, VFB1/2 = 0.6V 120 µA
ICOMP1/2-SINK EA sink current VCOMP1/2 = 1V, VFB1/2 = 1V 120 µA
VDRIVER1/2-DISABLE Drive output disable signal ISINK = 200µA, INTLV only 100 mV
POWER GOOD (PG1, PG2)
VPG1/2-OVP Power-Good overvoltage  Rising threshold 103 105 107 %
VPG1/2-OVP-HYST Power-Good OV hysteresis 1 %
VPG1/2-UVP Power-Good undervoltage protection Falling with respect to the regulated voltage 93 95 98 %
t-PG1/2-DEGLITCH(R) Power-Good deglitch rising 1.4 2 2.6 ms
t-PG1/2-DEGLITCH(F) Power-Good deglitch falling 60 90 120 µs
RON1/2(PG) PG1/2 on resistance Open drain, IPG = 250µA 100 250 Ω
SWITCHING FREQUENCY
FSW1 Switching frequency 1 RRT = 100kΩ to AGND 230 kHz
FSW2 Switching frequency 2 RRT = 10kΩ to AGND 1.98 2.2 2.42 MHz
FSW3 Switching frequency 3 RRT = 230kΩ to AGND 100 kHz
SLOPE1 Internal slope compensation 1 RRT = 10kΩ to AGND 480 mV/µs
SLOPE2 Internal slope compensation 2 RRT = 100kΩ to AGND 47 mV/µs
tON(min) Minimum on-time 15 35 ns
tOFF(min) Minimum off-time 45 65 ns
DMAX Maximum duty cycle 100 %
SYNCHRONIZATION OUTPUT (SYNCOUT)
VSYNCOUT-HO SYNCOUT high-state voltage ISYNCOUT = 4mA 2.0 V
VSYNCOUT-LO SYNCOUT low-state voltage ISYNCOUT = 4mA 0.8 V
tSYNCOUT1 Delay from HO1 rising edge to SYNCOUT rising edge VPFM/SYNC = 0V, TS = 1/FSW, FSW set by RRT = 230kΩ 2.5 µs
tSYNCOUT2 Delay from HO1 rising edge to SYNCOUT falling edge VPFM/SYNC = 0V, TS = 1/FSW, FSW set by RRT = 230kΩ 7.5 µs
PULSE FREQUENCY MODULATION (PFM/SYNC)
VPFM-LO PFM detection threshold low 0.8 V
VPFM-HI PFM detection threshold high 1.2 V
VZC-SW Zero-cross threshold –5.5 mV
FSYNCIN-MAX Maximum frequency sync range RRT = 10kΩ, ±20% of the nominal oscillator frequency 2640 kHz
FSYNCIN-MAX Minimum frequency sync range RRT = 10kΩ, ±20% of the nominal oscillator frequency 1760 kHz
tSYNC-MIN Minimum pulse-width of external synchronization  20 ns
tSYNCIN-HO Delay from SYNCIN rising edge to HO rising edge 70 ns
tPFM-FILTER SYNCIN to PFM mode 14 70 µs
CBOOT1, CBOOT2
VBOOT1/2-DROP Internal diode forward drop ICBOOT1/2 = 20mA, VCC to CBOOT 0.8 V
IBOOT1/2 CBOOT to SW quiescent current, not switching VEN1/2 = 5V, VCBOOT1/2 – VSW1/2 = 5V 2 µA
VBOOT1/2-SW-UV-R CBOOT to SW UVLO rising threshold VCBOOT1/2 – VSW1/2 rising 2.7 V
VBOOT1/2-SW-UV-F CBOOT to SW UVLO falling threshold VCBOOT1/2 – VSW1/2 falling 2.5 V
VBOOT1/2-SW-UV-HYS CBOOT to SW UVLO hysteresis 0.25 V
VCHARGE1/2–PUMP-UNLOADED Charge pump output voltage ICBOOT1/2 = 0 µA, per channel 4.8 V
ICHARGE1/2–PUMP Charge pump output current VCBOOT1/2 = 3.5V 20 µA
VCHARGE1/2–PUMP-LOADED Charge pump output voltage ICBOOT1/2 = 20µA, per channel 4.25 V
HIGH-SIDE GATE DRIVER (HO1, HO2)
VHO1/2-HIGH HO1/2 high-state output voltage IHO1/2 = –100mA 100 mV
VHO1/2-LOW HO1/2 low-state output voltage IHO1/2 = 100mA 45 mV
tHO1/2-RISE HO1/2 rise time (10% to 90%) CLOAD1/2 = 2.7nF 5.4 ns
tHO1/2-FALL HO1/2 fall time (90% to 10%) CLOAD1/2 = 2.7nF 4 ns
IHO1/2-SRC HO1/2 peak source current VHO1/2 = VSW1/2 = 0V  2 A
IHO1/2-SINK HO1/2 peak sink current VCBOOT1/2 = 5V 3 A
LOW-SIDE GATE DRIVER (LO1, LO2)
VLO1/2-HIGH LO1/2 high-state output voltage IHO1/2 = –100mA 100 mV
VLO1/2-LOW LO1/2 low-state output voltage IHO1/2 = 100mA 45 mV
ILO1/2-SRC LO1/2 peak source current VLO1/2 = VSW1/2 = 0V 2 A
ILO1/2-SINK LO1/2 peak sink current VVCC = 5V 3 A
ADAPTIVE DEADTIME CONTROL
tDEAD1 HO off to LO on deadtime 21 ns
tDEAD2 LO off to HO on deadtime 21 ns
START-UP
RSS1 1.5ms soft-start time RSS = 0Ω 1.25 ms
RSS2 2ms soft-start time RSS = 10kΩ 2.2 ms
RSS3 20ms soft-start time RSS = 100kΩ 22 ms
DUAL RANDOM SPREAD SPECTURM (DRSS)
fm1 Modulation frequency 7.2 16.8 kHz
ΔfSS1-LF Low-frequency triangular spread spectrum modulation range1 maximum –5 5 %
ΔfSS2-LF Low-frequency triangular spread spectrum modulation range2 maximum –10 10 %
OVERCURRENT PROTECTION 
VCS1/2-TH Current limit threshold Measured from ISNS1/2+ to VOUT1/2 54 60 66 mV
tDELAY1/2-ISNS+ ISNS+ delay from VCS-TH to HO off 70 ns
GCS1/2 CS amplifier gain 9.5 10 10.5 V/V
VCS-SHARE COMP to current accuracy VCOMP1/2 = 1.2V 54 60 66 mV
INTERNAL HICCUP MODE
HICDLY Hiccup mode activation delay VISNS1/2+ – VVOUT1/2 > 60 mV 512 cycles
HICTIME Hiccup mode duration VISNS1/2+ – VVOUT1/2 > 60 mV 16384 cycles
THERMAL SHUTDOWN
TSHD1/2 Thermal shutdown threshold Temperature rising 175 °C
TSHD-HYS1/2 Thermal shutdown hysteresis 15 °C