JAJSGF1C October   2018  – June 2021 LM5143-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Enable (EN1, EN2)
      4. 8.3.4  Power Good Monitor (PG1, PG2)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Clock Synchronization (DEMB)
      7. 8.3.7  Synchronization Out (SYNCOUT)
      8. 8.3.8  Spread Spectrum Frequency Modulation (DITH)
      9. 8.3.9  Configurable Soft Start (SS1, SS2)
      10. 8.3.10 Output Voltage Setpoint (FB1, FB2)
      11. 8.3.11 Minimum Controllable On-Time
      12. 8.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
      13. 8.3.13 Slope Compensation
      14. 8.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)
        1. 8.3.14.1 Shunt Current Sensing
        2. 8.3.14.2 Inductor DCR Current Sensing
      15. 8.3.15 Hiccup Mode Current Limiting (RES)
      16. 8.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)
      17. 8.3.17 Output Configurations (MODE, FB2)
        1. 8.3.17.1 Independent Dual-Output Operation
        2. 8.3.17.2 Single-Output Interleaved Operation
        3. 8.3.17.3 Single-Output Multiphase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Modes
      2. 8.4.2 Diode Emulation Mode
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency, Dual-Output Buck Regulator for Automotive Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 9.2.1.2.3 Inductor Calculation
          4. 9.2.1.2.4 Current-Sense Resistance
          5. 9.2.1.2.5 Output Capacitors
          6. 9.2.1.2.6 Input Capacitors
          7. 9.2.1.2.7 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedures
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate-Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)

The LM5143-Q1 contains N-channel MOSFET gate drivers and an associated high-side level shifter to drive the external N-channel MOSFET. The high-side gate driver works in conjunction with an external bootstrap diode DBST and bootstrap capacitor CBST. See Figure 8-7. During the conduction interval of the low-side MOSFET, the SW voltage is approximately 0 V and CBST is charged from VCC through DBST. TI recommends a 0.1-μF ceramic capacitor connected with short traces between the applicable HB and SW pins.

The LO and HO outputs are controlled with an adaptive dead-time methodology so that both outputs (HO and LO) are never enabled at the same time, preventing cross conduction. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below 2.5 V typical. LO is then enabled after a small delay (HO fall to LO rising delay). Similarly, the HO turnon is delayed until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO falling to HO rising delay). This technique ensures adequate dead time for any size N-channel MOSFET component or parallel MOSFET configurations.

Caution is advised when adding series gate resistors, as this can decrease the effective dead time. Each of the high-side and low-side drivers has an independent driver source and sink output pins. This allows the user to adjust drive strength to optimize the switching losses for maximum efficiency and control the slew rate for reduced EMI signature. The selected N-channel high-side MOSFET determines the appropriate bootstrap capacitance values CBST in Figure 8-7 according to Equation 14.

Equation 14. GUID-3226DE30-921C-4B2C-954B-EB2A4246ADC3-low.gif

where

  • QG is the total gate charge of the high-side MOSFET at the applicable gate drive voltage
  • ΔVBST is the voltage variation of the high-side MOSFET driver after turnon

To determine CBST, choose ΔVBST so that the available gate drive voltage is not significantly impacted. An acceptable range of ΔVBST is 100 mV to 300 mV. The bootstrap capacitor must be a low-ESR ceramic capacitor, typically 0.1 µF. Use high-side and low-side MOSFETs with logic level gate threshold voltages.

GUID-20210407-CA0I-LC3Q-VL2D-QW6R3B9WD8Q6-low.gif Figure 8-7 Integrated MOSFET Gate Drivers