JAJSGF1C October   2018  – June 2021 LM5143-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. 概要 (続き)
  6. Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Enable (EN1, EN2)
      4. 8.3.4  Power Good Monitor (PG1, PG2)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Clock Synchronization (DEMB)
      7. 8.3.7  Synchronization Out (SYNCOUT)
      8. 8.3.8  Spread Spectrum Frequency Modulation (DITH)
      9. 8.3.9  Configurable Soft Start (SS1, SS2)
      10. 8.3.10 Output Voltage Setpoint (FB1, FB2)
      11. 8.3.11 Minimum Controllable On-Time
      12. 8.3.12 Error Amplifier and PWM Comparator (FB1, FB2, COMP1, COMP2)
      13. 8.3.13 Slope Compensation
      14. 8.3.14 Inductor Current Sense (CS1, VOUT1, CS2, VOUT2)
        1. 8.3.14.1 Shunt Current Sensing
        2. 8.3.14.2 Inductor DCR Current Sensing
      15. 8.3.15 Hiccup Mode Current Limiting (RES)
      16. 8.3.16 High-Side and Low-Side Gate Drivers (HO1/2, LO1/2, HOL1/2, LOL1/2)
      17. 8.3.17 Output Configurations (MODE, FB2)
        1. 8.3.17.1 Independent Dual-Output Operation
        2. 8.3.17.2 Single-Output Interleaved Operation
        3. 8.3.17.3 Single-Output Multiphase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Modes
      2. 8.4.2 Diode Emulation Mode
      3. 8.4.3 Thermal Shutdown
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency, Dual-Output Buck Regulator for Automotive Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Custom Design With Excel Quickstart Tool
          3. 9.2.1.2.3 Inductor Calculation
          4. 9.2.1.2.4 Current-Sense Resistance
          5. 9.2.1.2.5 Output Capacitors
          6. 9.2.1.2.6 Input Capacitors
          7. 9.2.1.2.7 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Two-Phase, Single-Output Buck Regulator for Automotive ADAS Applications
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedures
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Stage Layout
      2. 11.1.2 Gate-Drive Layout
      3. 11.1.3 PWM Controller Layout
      4. 11.1.4 Thermal Design and Layout
      5. 11.1.5 Ground Plane Design
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
      3. 12.1.3 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
        1. 12.2.1.1 PCB Layout Resources
        2. 12.2.1.2 Thermal Design Resources
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 サポート・リソース
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Example

Based on the LM5143-Q1EVM-2100 design, Figure 11-2 shows a single-sided layout of a dual-output synchronous buck regulator. Each power stage is surrounded by a GND pad geometry to connect an EMI shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing. Refer to the LM5143-Q1EVM-2100 Evaluation Module User's Guide for more detail.

GUID-DEDD7472-82EB-4CDB-AE53-58CB4E7A58D4-low.gifFigure 11-2 PCB Top Layer

As shown in Figure 11-3, the high-frequency power loop current of one channel flows through MOSFETs Q2 and Q4, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors C16 through C19. The currents flowing in opposing directions in the vertical loop configuration provide field self-cancellation, reducing parasitic inductance. Figure 11-4 shows a side view to illustrate the concept of creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in Figure 11-3, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of Q2.

Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain of each high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency (SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of these capacitors are connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further minimizing parasitic loop inductance.

Additional steps used in this layout example include:

  • Keep the SW connection from the power MOSFETs to the inductor (for each channel) at minimum copper area to reduce radiated EMI.
  • Locate the controller close to the gate terminals of the MOSFETs such that the gate drive traces are routed short and direct.
  • Create an analog ground plane near the controller for sensitive analog components. The analog ground plane for AGND and power ground planes for PGND1 and PGND2 must be connected at a single point directly under the IC – at the die attach pad (DAP).
GUID-EDFEA9CD-409E-4B39-ADAF-80E33ACCAA87-low.gifFigure 11-3 Power Stage Component Layout
GUID-8139E6A1-58D8-4A42-932A-66216E45949A-low.gif Figure 11-4 PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing