JAJSFY2B August 2018 – June 2021 LM5146-Q1
PRODUCTION DATA
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The LM5146-Q1 implements a lossless current sense scheme designed to limit the inductor current during an overload or short-circuit condition. Figure 8-8 portrays the popular current sense method using the on-state resistance of the low-side MOSFET. Meanwhile, Figure 8-9 shows an alternative implementation with current shunt resistor, RS. The LM5146-Q1 senses the inductor current during the PWM off-time (when LO is high).
The ILIM pin of the LM5146-Q1 sources a reference current that flows in an external resistor, designated RILIM, to program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if the ILIM pin voltage goes below GND. Figure 8-10 shows the implementation.
Resistor RILIM is tied to SW to use the RDS(on) of the low-side MOSFET as a sensing element (termed RDS(on) mode). Alternatively, RILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed RSENSE mode). The LM5146-Q1 detects the appropriate mode at start-up and sets the source current amplitude and temperature coefficient (TC) accordingly.
The ILIM current with RDS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500 ppm/°C to generally track the RDS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM current is a constant 100 µA in RSENSE mode. This controls the valley of the inductor current during a steady-state overload at the output. Depending on the chosen mode, select the resistance of RILIM using Equation 6.
where
Given the large voltage swings of ILIM in RDS(on) sensing mode, a capacitor designated CILIM connected from ILIM to PGND is essential to the operation of the valley current limit circuit. Choose this capacitance such that the time constant RILIM· CILIM is approximately 6 ns.
Note that current sensing with a shunt component is typically implemented at lower output current levels to provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and additional cost implications, this configuration is not usually implemented in high-current applications (except where OCP setpoint accuracy and stability over the operating temperature range are critical specifications).