JAJSL66 february   2023 LM5148

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN)
      2. 8.3.2  High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
      3. 8.3.3  Precision Enable (EN)
      4. 8.3.4  Power-Good Monitor (PG)
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Dual Random Spread Spectrum (DRSS)
      7. 8.3.7  Soft Start
      8. 8.3.8  Output Voltage Setpoint (FB)
      9. 8.3.9  Minimum Controllable On Time
      10. 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
      11. 8.3.11 Slope Compensation
      12. 8.3.12 Inductor Current Sense (ISNS+, VOUT)
        1. 8.3.12.1 Shunt Current Sensing
        2. 8.3.12.2 Inductor DCR Current Sensing
      13. 8.3.13 Hiccup Mode Current Limiting
      14. 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
      15. 8.3.15 Output Configurations (CNFG)
      16. 8.3.16 Single-Output Dual-Phase Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
      2. 8.4.2 Pulse Frequency Modulation and Synchronization (PFM/SYNC)
      3. 8.4.3 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Train Components
        1. 9.1.1.1 Buck Inductor
        2. 9.1.1.2 Output Capacitors
        3. 9.1.1.3 Input Capacitors
        4. 9.1.1.4 Power MOSFETs
        5. 9.1.1.5 EMI Filter
      2. 9.1.2 Error Amplifier and Compensation
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High Efficiency 2.1-MHz Synchronous Buck Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Custom Design with Excel Quickstart Tool
          3. 9.2.1.2.3 Buck Inductor
          4. 9.2.1.2.4 Current-Sense Resistance
          5. 9.2.1.2.5 Output Capacitors
          6. 9.2.1.2.6 Input Capacitors
          7. 9.2.1.2.7 Frequency Set Resistor
          8. 9.2.1.2.8 Feedback Resistors
          9. 9.2.1.2.9 Compensation Components
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Efficiency 48-V to 12-V 400-kHz Synchronous Buck Regulator
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Design 3 – High Efficiency 440-kHz Synchronous Buck Regulator
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Design 4 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate-Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Custom Design with WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

TJ = –40°C to 125°C. Typical values are at TJ = 25°C and VIN = 12 V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY (VIN)
IQ-VIN1 VIN shutdown current VEN = 0 V 2.3 3.8 µA
IQ-VIN2 VIN standby current Non-switching, 0.5 V ≤ VEN ≤ 1 V 124 µA
ISLEEP1 Sleep current, 3.3 V 1.03 V ≤ VEN ≤  80 V, VVOUT = 3.3 V, in regulation, no-load, not switching, VPFM/SYNC = VDDA  9.5 19.7 µA
ISLEEP2 Sleep current, 5 V 1.03 V ≤ VEN ≤  80 V, VVOUT = 5.0 V, in regulation, no-load, not switching, VPFM/SYNC = VDDA 9.9 19.9 µA
ENABLE (EN)
VSDN Shutdown to standby threshold VEN rising 0.5 V
VEN-HIGH Enable voltage rising threshold VEN rising, enable switching 0.95 1.0 1.05 V
IEN-HYS Enable hysteresis VEN = 1.1 V –12 –10 –8 µA
INTERNAL LDO (VCC)
VVCC-REG VCC regulation voltage IVCC = 0 mA to 100 mA 4.7 5 5.3 V
VVCC-UVLO VCC UVLO rising threshold 3.3 3.4 3.5 V
VVCC-HYST VCC UVLO hysteresis 148 mV
IVCC-REG Internal LDO short-circuit current limit 115 170 mA
INTERNAL LDO (VDDA)
VVDDA-REG VDDA regulation voltage 4.75 5 5.25 V
VVDDA-UVLO VDDA UVLO rising VVCC rising, VVCCX = 0 V 3 3.2 3.3 V
VVDDA-HYST VDDA UVLO hysteresis  VVCCX = 0 V 120 mV
RVDDA VDDA resistance VVCCX = 0 V 5.5 Ω
EXTERNAL BIAS (VCCX)
VVCCX-ON VCCX rising threshold 4.1 4.3 4.4 V
VVCCX-HYST VCCX hysteresis voltage 130 mV
RVCCX VCCX resistance 2 Ω
REFERENCE VOLTAGE
VREF Regulated FB voltage 795 800 808 mV
OUTPUT VOLTAGE (VOUT)
VOUT-3.3V-INT 3.3-V output voltage setpoint RFB = 0 Ω, VIN = 3.8 V to 80 V, internal compensation 3.267 3.3 3.33 V
VOUT-3.3V-EXT 3.3-V output voltage setpoint RFB = 0 Ω, VIN = 3.8 V to 80 V, external compensation 3.267 3.3 3.33 V
VOUT-5V–INT 5-V output voltage setpoint
 		 RFB = 24.9 kΩ, VIN = 5.5 V to 80 V, internal compensation 4.95 5.0 5.05 V
VOUT-5V–EXT 5-V output voltage setpoint
 		 RFB = 24.9 kΩ, VIN = 5.5 V to 80 V, external compensation 4.95 5.0 5.05 V
VOUT-12V-INT 12-V output setpoint RFB = 48.7 kΩ, VIN = 24 V to 80 V, internal compensation 11.88 12 12.12 V
VOUT-12V-EXT 12-V output setpoint RFB = 48.7 kΩ, VIN = 24 V to 80 V, external compensation 11.88 12 12.12 V
RFB-OPT1 5-V output select 23 25 27 kΩ
RFB-OPT2 12-V output select 47 50 53 kΩ
ERROR AMPLIFIER (COMP)
gm-EXTERNAL EA transconductance, external compensation FB to COMP 1020 1200 µS
gm-INTERNAL EA transconductance, internal compensation EXTCOMP 10 kΩ to VDDA 30 µS
IFB Error amplifier input bias current 75 nA
VCOMP-CLAMP COMP clamp voltage VFB = 0 V 2.1 V
ICOMP-SRC EA source current VEXTCOMP = 1 V, VFB = 0.6 V 180 µA
ICOMP-SINK EA sink current VEXTCOMP = 1 V, VFB = 1 V 180 µA
RCOMP Internal compensation EXTCOMP 10 kΩ  to VDDA 400 kΩ
CCOMP Internal compensation EXTCOMP 10 kΩ  to VDDA 50 pF
CCOMP-HF Internal compensation EXTCOMP 10 kΩ  to VDDA 1 pF
PULSE FREQUENCY MODULATION (PFM/SYNC)
VPFM-LO PFM detection threshold low 0.8 V
VPFM-HI PFM decection threshold high 2.0 V
VZC-SW Zero-cross threshold –5.5 mV
VZC-DIS Zero-cross threshold disable PFM/SYNC = 0 V, 1000 SW cycles after first HO pulse 100 mV
FSYNCIN Frequency sync range RRT = 9.52 kΩ, ±20% of the nominal oscillator frequency 1.74 2.7 MHz
tSYNC-MIN Minimum pulse-width of external synchronization signal 20 250 ns
tSYNCIN-HO Delay from PFM faling edge to HO rising edge 45 ns
tPFM-FILTER SYNCIN to PFM mode 13 45 µs
DUAL RANDOM SPREAD SPECTRUM (DRSS)
ΔfC Switching frequency percentage change 7 %
fm Modulation frequency 8.2 16.2 kHz
SWITCHING FREQUENCY
VRT RT pin regulation voltage 10 kΩ < RRT < 100 kΩ 0.5 V
FSW1 Switching frequency 1  RRT = 97.6 kΩ to AGND  0.22 MHz
FSW2 Switching frequency 2 VIN = 12 V, RRT =  9.52 kΩ to AGND  1.98 2.2 2.42 MHz
FSW3 Switching frequency 3 RRT = 220 kΩ to AGND  100 kHz
SLOPE1 Internal slope compensation 1 RRT = 9.52 kΩ 600 mV/µs
SLOPE2 Internal slope compensation 2 RRT = 97.6 kΩ 50 mV/µs
tON(min) Minimum on-time 50 ns
tOFF(min) Minimum off-time 90 ns
POWER GOOD (PG)
VPG-UV Power Good UV trip level Falling with respect to the regulated voltage 90% 92%  94%
VPG-OV Power Good OV trip level  Rising with respect to the regulation voltage 108% 110% 112%
VPG-UV-HYST Power Good UV hysteresis  Rising with respect to the regulated output 3.6%
VPG-OV-HYST Power Good OV hysteresis Rising with respect to the regulation voltage 3.4%
tOV-DLY OV filter time VOUT rising 25 µs
tUV-DLY UV filter time VOUT falling 25 µs
VPG-OL PG voltage Open collector, PG/SYNC = 2 mA 0.8 V
SYNCHRONIZATION OUTPUT (PG/SYNCOUT)
VSYNCOUT-LO SYNCOUT-LO low-state voltage RCNFG = 54.9 kΩ or 71.5 kΩ to GND (primary), PFM/SYNC = 2 mA 0.8 V
VSYNCOUT-HO SYNCO-HO high-state voltage RCNFG = 54.9 kΩ, or 71.5 kΩ to GND (primary)  PFM/SYNC = 2 mA 2.0 V
tSYNCOUT Delay from HO rising edge to SYNCOUT (PG/SYNCOUT  in primary mode) VPFM = 0 V, FSW set by RRT = 97.6 kΩ 2.1 µs
STARTUP (Soft Start)
tSS-INT Internal fixed soft-start time 1.9 3 4.6 ms
BOOT CIRCUIT
VBOOT-DROP Internal diode forward drop ICBOOT = 20 mA, VCC to CBOOT 0.63 0.8 V
IBOOT CBOOT to SW quiescent current, not switching VEN = 5 V, VCBOOT-SW = 5 V 2.88 4.3 µA
VBOOT-SW-UV-R CBOOT to SW UVLO rising threshold VCBOOT-SW rising 2.83 V
VBOOT-SW-UV-F CBOOT to SW UVLO falling threshold VCBOOT-SW falling 2.5 V
VBOOT-SW-UV-HYS CBOOT to SW UVLO hysteresis 0.05 V
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH HO high-state output voltage IHO = –100 mA, VHO-HIGH = VCBOOT – VHO 106 mV
VHO-LOW HO low-state output voltage IHO = 100 mA 50 mV
tHO-RISE HO rise time (10% to 90%) CLOAD = 2.7 nF 7 ns
tHO-FALL HO fall time (90% to 10%) CLOAD = 2.7 nF 7 ns
IHO-SRC HO peak source current VHO = VSW = 0 V, VCBOOT = VVCC = 5 V 2.2 A
IHO-SINK HO peak sink current VVCC = 5 V 3.2 A
LOW-SIDE GATE DRIVER (LO)
VLO-LOW LO low-state output voltage ILO = 100 mA 50 mV
VLO-HIGH LO high-state output voltage ILO = –100 mA 130 mV
tLO-RISE LO rise time (10% to 90%) CLOAD = 2.7 nF 7 ns
tLO-FALL LO fall time (90% to 10%) CLOAD = 2.7 nF 7 ns
ILO-SRC LO peak source current VLO = VSW = 0 V, VVCC = 5 V 2.2 A
ILO-SINK LO peak sink current VVCC = 5 V 3.2 A
ADAPTIVE DEADTIME CONTROL
tDEAD1 HO off to LO on deadtime 20 ns
tDEAD2 LO off to HO on deadtime 20 ns
INTERNAL HICCUP MODE
HICDLY Hiccup mode activation delay VISNS+ –VVOUT > 60 mV 512 cycles
HICCYCLES HICCUP mode fault VISNS+ –VVOUT > 60 mV 16384 cycles
OVERCURRENT PROTECTION
VCS-TH Current limit threshold Measured from ISNS+ to VOUT 49 60 73 mV
tDELAY-ISNS+ ISNS+ delay to output 65 ns
GCS CS amplifier gain  9 10 10.8 V/V
IBIAS-ISNS+ CS amplifier input bias current  15 nA
CONFIGURATION
RCONF-OPT1 Primary, no spread spectrum 28.7 29.4 31 kΩ
RCONF-OPT2 Primary, with spread spectrum 40.2 41.2 43.2 kΩ
RCONF-OPT3 Primary, interleaved, no spread spectrum 53.6 54.9 57.6 kΩ
RCONF-OPT4 Primary, interleaved, with spread spectrum 69.8 71.5 73.2 kΩ
RCONF-OPT5 Secondary 87 90.9 93.1 kΩ
THERMAL SHUTDOWN
TJ-SD Thermal shutdown threshold (1) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis (1) 15 °C
(1) Specified by design. Not production tested.